Commit Graph

82076 Commits

Author SHA1 Message Date
Preston Gurd
c573b1f7ae Trivial change to set UseLeaForSP flag in addition to toggling
the FeatureLeaForSP feature bit when llvm auto detects Intel Atom.

Patch by Andy Zhang



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26 19:52:27 +00:00
Michael J. Spencer
3c00db75e1 [CMake] Restructure how Clang, Polly and other external projects get included.
While making lld build under the tools directory I decided to refactor how this
works.

There is now a macro, add_llvm_external_project, which takes the name of the
expected subdirectory. This sets up two CMake options.

 * LLVM_EXTERNAL_${NAME}_SOURCE_DIR
     This is the path to the source. It defaults to
     ${CMAKE_CURRENT_SOURCE_DIR}/${name}.
 * LLVM_EXTERNAL_${NAME}_BUILD
     Enable and disable building the tool as part of LLVM.

I chose LLVM_EXTERNAL_${NAME} as a prefix so they all show up together in the
GUI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155654 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26 19:43:35 +00:00
Michael J. Spencer
60f3d92b2a [Support/YAML] Properly fix unitialized variable warning by inserting a
'REPLACEMENT CHARACTER' (U+FFFD) when getAsInteger fails.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155653 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26 19:27:11 +00:00
Stepan Dyatkovskiy
5c77bc29db Fixed SmallMap test. The order of items is undefined in DenseMap. So being checking the increment for big mode, we can only check that all items are in map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155651 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26 18:45:24 +00:00
Tim Northover
37abe8df4a Use VLD1 in NEON extenting-load patterns instead of VLDR.
On some cores it's a bad idea for performance to mix VFP and NEON instructions
and since these patterns are NEON anyway, the NEON load should be used.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155630 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26 08:46:29 +00:00
Tim Northover
e38993f892 Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155626 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26 08:24:07 +00:00
Craig Topper
1203f2f138 Enable detection of AVX and AVX2 support through CPUID. Add AVX/AVX2 to corei7-avx, core-avx-i, and core-avx2 cpu names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155618 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26 06:40:15 +00:00
Chandler Carruth
464bda3a16 Teach the reassociate pass to fold chains of multiplies with repeated
elements to minimize the number of multiplies required to compute the
final result. This uses a heuristic to attempt to form near-optimal
binary exponentiation-style multiply chains. While there are some cases
it misses, it seems to at least a decent job on a very diverse range of
inputs.

Initial benchmarks show no interesting regressions, and an 8%
improvement on SPASS. Let me know if any other interesting results (in
either direction) crop up!

Credit to Richard Smith for the core algorithm, and helping code the
patch itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155616 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26 05:30:30 +00:00
Evan Cheng
cac31de146 Specify cpu to unbreak tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155604 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26 01:38:10 +00:00
Evan Cheng
e67a4163f5 If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assume
the feature set of v7a. This comes about if the user specifies something like
-arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as
uxtab in this case.

rdar://11318438


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155601 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26 01:13:36 +00:00
Bill Wendling
4866363304 Don't forget to reset 'first operand' flag when we're setting the MDNodeOperand value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155599 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26 00:38:42 +00:00
Jakob Stoklund Olesen
6962106496 Try to fix llvm-arm-linux builder with -mcpu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155589 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 21:22:33 +00:00
Preston Gurd
01c0dd1be3 Trivial change to make the test use -mcpu=generic so as to avoid
a failure if run on an Intel Atom with post RA instruction scheduling.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155587 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 21:04:54 +00:00
Benjamin Kramer
b856d555b0 Reapply the SmallMap patch with a fix.
Comparing ~0UL with an unsigned will always return false when long is 64 bits long.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155568 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 18:01:58 +00:00
Jakob Stoklund Olesen
165324cd7d Print IV chain numbers while collecting them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155567 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 18:01:32 +00:00
Jakob Stoklund Olesen
a0b0219a9e Remove more dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155566 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 18:01:30 +00:00
Richard Barton
b56e4115ed Unify internal representation of ARM instructions with a register right-shifted by #32. These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155565 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 18:00:18 +00:00
Eric Christopher
bdbf015476 Revert "First implementation of:"
This reverts commit 76271a3366.

as it's breaking the bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155562 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 17:51:00 +00:00
Stepan Dyatkovskiy
76271a3366 First implementation of:
- FlatArrayMap. Very simple map container that uses flat array inside.
- MultiImplMap. Map container interface, that has two modes, one for small amount of elements and one for big amount.
- SmallMap. SmallMap is DenseMap compatible MultiImplMap. It uses FlatArrayMap for small mode, and DenseMap for big mode. 

Also added unittests for new classes and update for ProgrammersManual.
For more details about new classes see ProgrammersManual and comments in sourcecode.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155557 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 17:09:38 +00:00
Jakob Stoklund Olesen
50e1d84ba8 Simplify LiveIntervals::getApproximateInstructionCount().
This function is only used for a heuristic during -join-physregs. It
doesn't need floating point.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155554 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 16:32:23 +00:00
Jakob Stoklund Olesen
a62efd82cc Remove a dead function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155553 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 16:32:20 +00:00
Jakob Stoklund Olesen
40a2b653e1 Remove the -disable-cross-class-join option.
Cross-class joins have been normal and fully supported for a while now.
With TableGen generating the getMatchingSuperRegClass() hook, they are
unlikely to cause problems again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155552 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 16:17:50 +00:00
Jakob Stoklund Olesen
a2404e3458 Cross-class joining is winning.
Remove the heuristic for disabling cross-class joins. The greedy
register allocator can handle the narrow register classes, and when it
splits a live range, it can pick a larger register class.

Benchmarks were unaffected by this change.

<rdar://problem/11302212>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155551 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 16:17:47 +00:00
Craig Topper
8030e1a0df Add ifdef around getSubtargetFeatureName in tablegen output file so that only targets that want the function get it. This prevents other targets from getting an unused function warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155538 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 06:56:34 +00:00
Craig Topper
c16f851569 Use vector_shuffles instead of target specific unpack nodes for AVX ZERO_EXTEND/ANY_EXTEND combine. These will be converted to target specific nodes during lowering. This is more consistent with other code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155537 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 06:39:39 +00:00
Chris Lattner
fa1059fd9c openbsd doesn't support soname, patch by Brad Smith!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155536 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 06:37:20 +00:00
Chandler Carruth
3ef91f575e Actually delete now-empty file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155532 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 02:30:00 +00:00
Lang Hames
87aac6a877 Reverting r155468. Chris and Chandler have convinced me that it's dangerous and
in poor taste.

Talking through some alternate solutions with Chandler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155530 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 02:16:54 +00:00
Akira Hatanaka
25052f4077 Do not use $gp as a dedicated global register if the target ABI is not O32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155522 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 01:24:52 +00:00
Andrew Trick
23d59c2fb8 typo in declaration from earlier today
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155519 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 01:11:22 +00:00
Dan Gohman
50ade65982 Simplify the known retain count tracking; use a boolean state instead
of a precise count. Also, move RRInfo's Partial field into PtrState,
now that it won't increase the size.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155513 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 00:50:46 +00:00
Dan Gohman
eeeb7752a8 Build custom predecessor and successor lists for each basic block.
These lists exclude invoke unwind edges and loop backedges which
are being ignored. This makes it easier to ignore them
consistently.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155500 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 22:53:18 +00:00
Jim Grosbach
14ce6fac24 ARM: improved assembler diagnostics for missing CPU features.
When an instruction match is found, but the subtarget features it
requires are not available (missing floating point unit, or thumb vs arm
mode, for example), issue a diagnostic that identifies what the feature
mismatch is.

rdar://11257547

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155499 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 22:40:08 +00:00
Andrew Trick
86b7e2acc9 Fix a naughty header include that breaks "installed" builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155486 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 20:36:19 +00:00
Nadav Rotem
80c1ea6f9b ConstantFoldSelectInstruction swapped the operands of the select.
Fix 12592. Patch by Matt Pharr.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155480 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 20:18:49 +00:00
Nadav Rotem
2003e03045 Fix the testcase. We do expect two vblendw on XMMs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155477 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 19:57:38 +00:00
Nadav Rotem
34a13bb412 Add a testcase for 155440
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155475 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 19:45:28 +00:00
Evan Cheng
ddb1420e17 MachineBasicBlock::SplitCriticalEdge() should follow LLVM IR variant and refuse to break edge to EH landing pad. rdar://11300144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155470 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 19:06:55 +00:00
Lang Hames
1d9e68dab1 Add support for llvm.arm.neon.vmull* intrinsics to InstCombine. This fixes
<rdar://problem/11291436>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155468 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 18:58:36 +00:00
Chandler Carruth
7362ac7f8c Fix a crash on valid (if UB) bitcode that is produced for some global
constants in C++11 mode. I have no idea why it required such particular
circumstances to get here, the code seems clearly to rely upon unchecked
assumptions.

Specifically, when we decide to form an index into a struct type, we may
have gone through (at least one) zero-length array indexing round, which
would have left the offset un-adjusted, and thus not necessarily valid
for use when indexing the struct type.

This is just an canonicalization step, so the correct thing is to refuse
to canonicalize nonsensical GEPs of this form. Implemented, and test
case added.

Fixes PR12642. Pair debugged and coded with Richard Smith. =] I credit
him with most of the debugging, and preventing me from writing the wrong
code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155466 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 18:42:47 +00:00
Jim Grosbach
95a7e80b5e ARM: Nuke remnant bogus code.
r154362 was supposed to delete this bit, but obviously didn't.

rdar://11305594

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155465 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 18:39:47 +00:00
Stepan Dyatkovskiy
6ce1c88a4f Related to PR1255. Let's begin. I'll commit classes that corresponds to our latest PR1255 discussion posts in llvm-commits.
Strategy.
0. Implement new classes. Classes doesn't affect anything. They still work with ConstantInt base values at this stage.
1. Fictitious replacement of current ConstantInt case values with ConstantRangesSet. Case ranges set will still hold single value, and ConstantInt *getCaseValue() will return it. But additionally implement new method in SwitchInst that allows to work with case ranges. Currenly I think it should be some wrapper that returns either single value or ConstantRangesSet object.
2. Step-by-step replacement of old "ConstantInt* getCaseValue()" with new alternative. Modify algorithms for all passes that works with SwitchInst. But don't modify LLParser and BitcodeReader/Writer. Still hold single value in each ConstantRangesSet object. On this stage some parts of LLVM will use old-style methods, and some ones new-style.
3. After all getCaseValue() usages will removed and whole LLVM and its clients will work in new style - modify LLParser, Reader and Writer. Remove getCaseValue().
4. Replace ConstantInt*-based case ranges set items with APInt ones.

Currently we are on Zero Stage: New classes.
ConstantRangesSet.
I selected ConstantArrays as case ranges set "holder" object (it is a temporary decision, I'll explain why below). The array items are may be ConstantVectors with single item, and ConstantVectors with two items (that means single number and range respectively).
The ConstantInt will used as basic value representation. It will replaced with APInt then. Of course ConstantArray and ConstantVector will go away after ConstantInt => APInt replacement.

New class mandatory features:
- bool isSatisfies(ConstantInt *V) method (need better name?). Returns true if the given value satisfies this case.
- Case's ranges and values enumeration. In some passes we need to analize each case (SwitchLowering for example).

Factory + unified clusterify.
I also propose to implement the factory that allows to build case object with user friendly way. I called it CRSBuilder by now.
Currenly I implemented the factory that allows add,remove pairs of range+successor. It also allows add existing ConstantRangesSet decompiling it to separated ranges. Factory can emit either clusters set (single case range + successor) or the set of "ConstantRangesSet + Successor" pairs.
So you can use it either as builder for new cases set for SwitchInst, or for clusterification of existing cases set.
Just call Factory.optimize() and it emits optimized and sorted clusters collection for you!
I tested clusterification on SelectionDAGBuilder - it works fine. Don't worry it was not included in this patch. Just new classes.
Factory is a template. There are two params: SuccessorClass and IsReadonly. So you can specify what successor you need (BB or MBB). And you can also restrict your factory to use values in read-only mode (SelectionDAGBuilder need IsReadonly=true). Read-only factory couldn't build the cases ranges.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155464 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 18:31:10 +00:00
Nadav Rotem
7bc9698f3a AVX: Add additional vbroadcast replacement sequences for integers.
Remove the v2f64 patterns because it does not match any vbroadcast
instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155461 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 18:09:59 +00:00
Andrew Trick
63bbe14e20 cmake: new file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 18:06:49 +00:00
Andrew Trick
c3ad885dac misched: DAG builder must special case earlyclobber
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155459 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 18:04:41 +00:00
Andrew Trick
000b2504ee misched: try (not too hard) to place debug values where they belong
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155458 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 18:04:37 +00:00
Andrew Trick
eb45ebbdef misched: ignore debug values during scheduling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155457 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 18:04:34 +00:00
Andrew Trick
006e1abf76 misched: DAG builder support for tracking register pressure within the current scheduling region.
The DAG builder is a convenient place to do it. Hopefully this is more
efficient than a separate traversal over the same region.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155456 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 17:56:43 +00:00
Andrew Trick
4dfeef100d RegisterPressure: A utility for computing register pressure within a
MachineInstr sequence.

This uses the new target interface for tracking register pressure
using pressure sets to model overlapping register classes and
subregisters.

RegisterPressure results can be tracked incrementally or stored at
region boundaries. Global register pressure can be deduced from local
RegisterPressure results if desired.

This is an early, somewhat untested implementation. I'm working on
testing it within the context of a register pressure reducing
MachineScheduler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155454 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 17:53:35 +00:00
Kevin Enderby
24e767d076 Add missing test cases for ARM VLD3 (single 3-element structure to all lanes)
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155453 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 17:45:56 +00:00