Commit Graph

26396 Commits

Author SHA1 Message Date
Akira Hatanaka
c746503425 [mips] Disable tail merging when long branch pass is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192124 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 19:13:53 +00:00
Benjamin Kramer
51a8280fbb X86: Fix type check. Just because an integer type is illegal doesn't mean it's i64.
Fixes PR17495, where an i24 triggered this code. It's intended to
optimize i64 loads on 32 bit x86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 19:11:35 +00:00
Akira Hatanaka
96ba8cb9b2 [mips] Define method MipsSubtarget::enableLongBranchPass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192122 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 19:06:57 +00:00
Akira Hatanaka
243702b95a [mips] Fix definition of mfhi and mflo instructions to read from the whole
accumulator instead of its sub-registers, $hi and $lo. 

We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:

mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2     // read lower 32-bit result from $lo.
mtlo $4     // write to $lo. the content of $hi becomes unpredictable.
mfhi $3     // read higher 32-bit from $hi, which has an unpredictable value.

I don't have a test case for this change that reliably reproduces the problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192119 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 18:49:46 +00:00
Amara Emerson
ca7b2d08d7 [ARM] Improve build attributes emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192111 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 16:55:23 +00:00
Chad Rosier
2aeb4771a6 [AArch64] Add support for NEON scalar arithmetic instructions:
SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192107 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 16:36:15 +00:00
Rafael Espindola
ef8c4ca252 Remove getEHExceptionRegister and getEHHandlerRegister.
They haven't been used for a long time. Patch by MathOnNapkins.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192099 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 13:39:22 +00:00
Tim Northover
cf3e4cb29a ARM: allow cortex-m0 to use hint instructions
The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have
been ported across to the v6M architecture. Fortunately, v6M seems to sit
nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it
fairly easily.

rdar://problem/15144406

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192097 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 11:10:47 +00:00
Craig Topper
e778f82a1e Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192090 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 07:19:47 +00:00
Craig Topper
510fb362a8 Remove FsMOVAPSrr and friends. They have no patterns and are no longer selected anywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192089 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 06:10:45 +00:00
Craig Topper
8fdba75d5b Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not.
This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior and instruction selection already does this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192088 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 05:42:48 +00:00
Craig Topper
36a9b31b98 Add disassembler support for long encodings for INC/DEC in 32-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192086 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 04:28:06 +00:00
Benjamin Kramer
d9f7a185e3 X86: Don't fold spills into SSE operations if the stack is unaligned.
Regalloc can emit unaligned spills nowadays, but we can't fold the
spills into SSE ops if we can't guarantee alignment. PR12250.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192064 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-06 13:48:22 +00:00
Elena Demikhovsky
714319a169 AVX-512: added scalar convert instructions and intrinsics.
Fixed load folding in VPERM2I instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192063 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-06 13:11:09 +00:00
Venkatraman Govindaraju
79c5e0c5ca [Sparc] Do not emit nop after fcmp* instruction with V9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192056 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-06 07:06:44 +00:00
Elena Demikhovsky
a6269ee5fb AVX-512: fixed shuffle lowering
in case of BLEND and added VSHUFPS patterns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192055 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-06 06:11:18 +00:00
Venkatraman Govindaraju
20b10abf4e [Sparc] Custom lower addc/adde/subc/sube on i64 in sparc64.
This is required because i64 is a legal type but addxcc/subxcc reads icc carry bit, which are 32 bit conditional codes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192054 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-06 03:36:18 +00:00
Venkatraman Govindaraju
bb0ec9840b [Sparc] Use addxcc/subxcc for adde/sube instead of addx/subx.
addx/subx does not modify conditional codes whereas addxcc/subxx does.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192053 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-06 02:11:10 +00:00
Craig Topper
984fbe6c65 Add TBM instructions to loading folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192046 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 20:20:51 +00:00
Nick Lewycky
e66dd40d74 Rename this feature to "cx16" to match gcc's flag name. Apparently these strings
are directly tied to the flag names in clang with no remapping in between?


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192044 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 20:11:44 +00:00
Craig Topper
617ba175da Remove underscores from TBM instruction names for consistency with other instruction naming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192040 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 19:27:26 +00:00
Craig Topper
22abf7e17f Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns are sufficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192039 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 19:22:59 +00:00
Craig Topper
e2522fd06c Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into (sub -2, x).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192037 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 17:17:53 +00:00
Rafael Espindola
5e195a4c8d Remove some really nasty uses of hasRawTextSupport.
When MC was first added, targets could use hasRawTextSupport to keep features
working before they were added to the MC interface.

The design goal of MC is to provide an uniform api for printing assembly and
object files. Short of relaxations and other corner cases, a object file is
just another representation of the assembly.

It was never the intention that targets would keep doing things like

if (hasRawTextSupport())
  Set flags in one way.
else
  Set flags in another way.

When they do that they create two code paths and the object file is no longer
just another representation of the assembly. This also then requires testing
with llc -filetype=obj, which is extremelly brittle.

This patch removes some of these hacks by replacing them with smaller ones.
The ARM flag setting is trivial, so I just moved it to the constructor. For
Mips, the patch adds two temporary hack directives that allow the assembly
to represent the same things as the object file was already able to.

The hope is that the mips developers will replace the hack directives with
the same ones that gas uses and drop the -print-hack-directives flag.

I will also try to implement a target streamer interface, so that we can
move this out of the common code.

In summary, for any new work, two rules of the thumb are
  * Don't use "llc -filetype=obj" in tests.
  * Don't add calls to hasRawTextSupport.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192035 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 16:42:21 +00:00
Jiangning Liu
beb6afa843 Implement aarch64 neon instruction set AdvSIMD (Across).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192028 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 08:22:10 +00:00
Venkatraman Govindaraju
a8147756d6 [Sparc] Use correct alignment while loading/storing fp128 values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192023 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 02:29:47 +00:00
Venkatraman Govindaraju
b648122c5f [Sparc] Respect hasHardQuad parameter correctly when lowering SINT_TO_FP with fp128 operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192015 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 00:31:41 +00:00
Venkatraman Govindaraju
1c9524b624 [Sparc] Correct the floating point conditional code mapping in GetOppositeBranchCondition().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192006 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 23:54:30 +00:00
Jack Carter
596654bd10 forgot to remove this file as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191993 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 22:54:05 +00:00
Jack Carter
6d389f5eba reverting per request
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191992 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 22:52:31 +00:00
Reed Kotler
5404ed811d Support tblockaddr for static compilation in Mips16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 22:01:40 +00:00
Jack Carter
8e48edcf3d [MC][AsmParser] Hook for post assembly file processing
This patch handles LLVM standalone assembler (llvm-mc) ELF flag setting based on input file
directive processing.

Mips assembly requires processing inline directives that directly and
indirectly affect the output ELF header flags. This patch handles one
".abicalls".

To process these directives we are following the model the code generator
uses by storing state in a container as we go through processing and when
we detect the end of input file processing, AsmParser is notified and we
update the ELF header flags through a MipsELFStreamer method with a call from
MCTargetAsmParser::emitEndOfAsmFile(MCStreamer &OutStreamer).

This patch will allow other targets the same functionality.

Jack


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191982 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 21:26:15 +00:00
Akira Hatanaka
60ccc3b0ec [mips] Fix a bug in MipsLongBranch::replaceBranch, which was erasing
instructions in delay slots along with the original branch instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191978 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 20:51:40 +00:00
Matthias Braun
d1bd8d904c ARM: optimizeSelect has to consider the previous register class
optimizeSelect folds (predicated) copy instructions, it must not ignore
the original register class of the operand when replacing the register
with the copies dest register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191963 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 16:52:56 +00:00
Matthias Braun
4e54f41d6c ARM: do not add a regmask for TAILJUMPs
The jump doesn't really kill the registers, the following call does but
we never get back anyway.
This avoids some verify-machineinstrs problems when TAILJUMPs are
if-converted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191962 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 16:52:54 +00:00
Matthias Braun
e1bde51d63 ARM: preserve undef flag in pseudo instruction expanders
Copy over the whole register machine operand instead of creating a new one
with an incomplete set of flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191961 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 16:52:51 +00:00
Jiangning Liu
dd518bcc9d Implement aarch64 neon instruction set AdvSIMD (3V elem).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191944 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 09:20:44 +00:00
Elena Demikhovsky
5086ff1320 AVX-512: Fixed encoding of VMOVQ instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191889 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-03 12:03:26 +00:00
Amara Emerson
6eef361b73 [ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.
Patch by Artyom Skrobov.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191885 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-03 09:31:51 +00:00
Craig Topper
198f1b340a Replace C++ style comment with a C style comment to satisfy some of the build bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191880 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-03 06:29:59 +00:00
Craig Topper
e3b0a9c51a Remove comma from the end of an enum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191877 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-03 06:18:26 +00:00
Craig Topper
279d28265d Add XOP disassembler support. Fixes PR13933.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191874 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-03 05:17:48 +00:00
Craig Topper
fafe4bbd6c Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191871 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-03 04:16:45 +00:00
Vincent Lejeune
a2f1317f09 R600: Add a ldptr intrinsic to support MSAA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191838 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-02 16:00:33 +00:00
Elena Demikhovsky
c699417f11 AVX-512: fixed a bug in getLoadStoreRegOpcode() for AVX-512 target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191818 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-02 12:20:42 +00:00
Elena Demikhovsky
d243c19c1f AVX-512: Added TB prefix to all instructions without prefixes,
otherwise encoding fails after the last change in X86MCCodeEmitter.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191812 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-02 06:39:07 +00:00
Vincent Lejeune
dfef7cbfc6 R600: add a pass that merges clauses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191790 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 19:32:58 +00:00
Vincent Lejeune
c6c37d74a2 R600: Put PRED_X instruction in its own clause
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191789 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 19:32:49 +00:00
Vincent Lejeune
5b00e833fa R600: Enable -verify-machineinstrs in some tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191788 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 19:32:38 +00:00
Richard Sandiford
e22c56d6d8 [SystemZ] Add comparisons of high words and memory
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191777 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 15:00:44 +00:00