Commit Graph

442 Commits

Author SHA1 Message Date
Evan Cheng
c781a243a3 In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all.
VirtRegMap keeps track of allocations so it knows what's not used. As a horrible hack, the stack coloring can color spill slots with *free* registers. That is, it replace reload and spills with copies from and to the free register. It unfold instructions that load and store the spill slot and replace them with register using variants.

Not yet enabled. This is part 1. More coming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70787 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-03 18:32:42 +00:00
Evan Cheng
c45288e06b Fix PR4076. Correctly create live interval of physical register with two-address update.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70245 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27 20:42:46 +00:00
Evan Cheng
d521bc983b Fix PR4056. It's possible a physical register def is dead if its implicit use is deleted by two-address pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70213 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27 17:36:47 +00:00
Evan Cheng
5b69ebac85 It has finally happened. Spiller is now using live interval info.
This fixes a very subtle bug. vr defined by an implicit_def is allowed overlap with any register since it doesn't actually modify anything. However, if it's used as a two-address use, its live range can be extended and it can be spilled. The spiller must take care not to emit a reload for the vn number that's defined by the implicit_def. This is both a correctness and performance issue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69743 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-21 22:46:52 +00:00
Evan Cheng
206d1856ad Added a linearscan register allocation optimization. When the register allocator spill an interval with multiple uses in the same basic block, it creates a different virtual register for each of the reloads. e.g.
%reg1498<def> = MOV32rm %reg1024, 1, %reg0, 12, %reg0, Mem:LD(4,4) [sunkaddr39 + 0]
        %reg1506<def> = MOV32rm %reg1024, 1, %reg0, 8, %reg0, Mem:LD(4,4) [sunkaddr42 + 0]
        %reg1486<def> = MOV32rr %reg1506
        %reg1486<def> = XOR32rr %reg1486, %reg1498, %EFLAGS<imp-def,dead>
        %reg1510<def> = MOV32rm %reg1024, 1, %reg0, 4, %reg0, Mem:LD(4,4) [sunkaddr45 + 0]

=>

        %reg1498<def> = MOV32rm %reg2036, 1, %reg0, 12, %reg0, Mem:LD(4,4) [sunkaddr39 + 0]
        %reg1506<def> = MOV32rm %reg2037, 1, %reg0, 8, %reg0, Mem:LD(4,4) [sunkaddr42 + 0]
        %reg1486<def> = MOV32rr %reg1506
        %reg1486<def> = XOR32rr %reg1486, %reg1498, %EFLAGS<imp-def,dead>
        %reg1510<def> = MOV32rm %reg2038, 1, %reg0, 4, %reg0, Mem:LD(4,4) [sunkaddr45 + 0]

From linearscan's point of view, each of reg2036, 2037, and 2038 are separate registers, each is "killed" after a single use. The reloaded register is available and it's often clobbered right away. e.g. In thise case reg1498 is allocated EAX while reg2036 is allocated RAX. This means we end up with multiple reloads from the same stack slot in the same basic block.

Now linearscan recognize there are other reloads from same SS in the same BB. So it'll "downgrade" RAX (and its aliases) after reg2036 is allocated until the next reload (reg2037) is done. This greatly increase the likihood reloads from SS are reused.

This speeds up sha1 from OpenSSL by 5.8%. It is also an across the board win for SPEC2000 and 2006.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69585 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-20 08:01:12 +00:00
Dan Gohman
70f2f65aac Don't abort on an aliasing physical register that does not have
a live interval. This is needed for some upcoming subreg changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68956 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 15:22:29 +00:00
Bob Wilson
d9df501704 Fix pr3954. The register scavenger asserts for inline assembly with
register destinations that are tied to source operands.  The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly.  The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68714 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-09 17:16:43 +00:00
Dan Gohman
97121ba2af Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.

This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.

Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.

Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.

Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.

Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68576 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08 00:15:30 +00:00
Owen Anderson
b98bbb7597 Don't assign a new stack slot if the pre-alloc splitter already assigned one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67764 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-26 18:53:38 +00:00
Evan Cheng
2824a65550 Fix PR3391 and PR3864. Reg allocator infinite looping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67544 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23 18:24:37 +00:00
Evan Cheng
fb11288109 Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67512 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23 08:01:15 +00:00
Sebastian Redl
48fe63526e Fix the Win32 VS2008 build:
- Make type declarations match the struct/class keyword of the definition.
 - Move AddSignalHandler into the namespace where it belongs.
 - Correctly call functions from template base.
 - Some other small changes.
With this patch, LLVM and Clang should build properly and with far less noise under VS2008.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67347 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-19 23:26:52 +00:00
Evan Cheng
a24752ff43 Added MachineInstr::isRegTiedToDefOperand to check for two-addressness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67335 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-19 20:30:06 +00:00
Evan Cheng
0076c616e8 Fix how livein live intervals are handled. Previously it could end at MBB start. Sorry, no small test case possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66129 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-05 03:34:26 +00:00
Evan Cheng
0a1fcce092 Fix PR3486. Fix a bug in code that manually patch physical register live interval after its sub-register is coalesced with a virtual register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64082 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-08 11:04:35 +00:00
Evan Cheng
5a3c6a87b0 Exit with nice warnings when register allocator run out of registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63267 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-29 02:20:59 +00:00
Evan Cheng
04ee5a1d92 Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-20 19:12:24 +00:00
Evan Cheng
8f90b6eb2f The coalescer does not coalesce a virtual register to a physical register if any of the physical register's sub-register live intervals overlaps with the virtual register. This is overly conservative. It prevents a extract_subreg from being coalesced away:
v1024 = EDI  // not killed
      =
      = EDI

One possible solution is for the coalescer to examine the sub-register live intervals in the same manner as the physical register. Another possibility is to examine defs and uses (when needed) of sub-registers. Both solutions are too expensive. For now, look for "short virtual intervals" and scan instructions to look for conflict instead.

This is a small win on x86-64. e.g. It shaves 403.gcc by ~80 instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61847 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-07 02:08:57 +00:00
Evan Cheng
5379f412bc Fix PR3149. If an early clobber def is a physical register and it is tied to an input operand, it effectively extends the live range of the physical register. Currently we do not have a good way to represent this.
172     %ECX<def> = MOV32rr %reg1039<kill>
180     INLINEASM <es:subl $5,$1
        sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9, %EAX<kill>,
36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0
188     %EAX<def> = MOV32rr %EAX<kill>
196     %ECX<def> = MOV32rr %ECX<kill>
204     %ECX<def> = MOV32rr %ECX<kill>
212     %EAX<def> = MOV32rr %EAX<kill>
220     %EAX<def> = MOV32rr %EAX
228     %reg1039<def> = MOV32rr %ECX<kill>

The early clobber operand ties ECX input to the ECX def.

The live interval of ECX is represented as this:
%reg20,inf = [46,47:1)[174,230:0)  0@174-(230) 1@46-(47)

The right way to represent this is something like
%reg20,inf = [46,47:2)[174,182:1)[181:230:0)  0@174-(182) 1@181-230 @2@46-(47)

Of course that won't work since that means overlapping live ranges defined by two val#.

The workaround for now is to add a bit to val# which says the val# is redefined by a early clobber def somewhere. This prevents the move at 228 from being optimized away by SimpleRegisterCoalescing::AdjustCopiesBackFrom.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61259 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-19 20:58:01 +00:00
Dan Gohman
c93ced5b34 Clarify some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60683 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-08 04:53:23 +00:00
Evan Cheng
650d7f3ff4 Reason #3 from 60595 doesn't hold true. If we can fold a PIC load from constpool into a use, the rewrite happens at time of spill (not in VirtRegMap). Later on, if the GlobalBaseReg is spilled, the spiller can see the use uses GlobalBaseReg and do the right thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60596 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-05 17:41:31 +00:00
Evan Cheng
72eeb94fe1 Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60592 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-05 17:00:16 +00:00
Dan Gohman
2ce7f2068f Drop the reg argument to isRegReDefinedByTwoAddr, which was redundant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60586 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-05 05:45:42 +00:00
Dan Gohman
15511cf166 Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-03 18:15:48 +00:00
Dan Gohman
2ad8245566 LiveRanges are represented as half-open ranges. Fix the findLiveInMBBs code
and the LiveInterval.h top-level comment and accordingly. This fixes blocks
having spurious live-in registers in boundary cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60092 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-26 05:50:31 +00:00
Devang Patel
59500c8f9a Silence unused variable warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59841 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-21 20:00:59 +00:00
Dan Gohman
4a829ecc54 Use find_first/find_next to iterate through all the set bits in a
BitVector, instead of manually testing each bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59246 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 16:31:27 +00:00
Dan Gohman
4cbb3ca67d Remove some debugging code made redundant by the change to do
coalescing as a separate pass rather than inside of
LiveIntervalAnalysis.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-12 17:09:23 +00:00
Evan Cheng
d0e32c5d5c - Rewrite code that update register live interval that's split.
- Create and update spill slot live intervals.
- Lots of bug fixes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58367 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-29 05:06:14 +00:00
David Greene
26b86a0b56 Fix PR2634. Create new virtual registers from spills early so that we
can give it the same stack slot as the spilled interval if it is folded.
This prevents the fold/unfold code from pointing to the wrong register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58255 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-27 17:38:59 +00:00
Evan Cheng
06587497dc Avoid splitting an interval multiple times; avoid splitting re-materializable val# (for now).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58068 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-24 02:05:00 +00:00
Evan Cheng
4ed4329c37 By min, I mean max.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57766 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-18 05:21:37 +00:00
Evan Cheng
99fe34b9b2 When creating intervals, leave min(1, numdefs) holes after each instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57765 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-18 05:18:55 +00:00
Owen Anderson
95dad830bb Add an option to enable StrongPHIElimination, for ease of testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57259 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-07 20:22:28 +00:00
Dan Gohman
d735b8019b Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-03 15:45:36 +00:00
Owen Anderson
309c6162c6 Fix a simple error in renumbering kill markaers, that took an inordinant amount of time to track down.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56889 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-30 22:51:54 +00:00
Evan Cheng
dc37786595 Re-apply 56835 along with header file changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56848 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-30 15:44:16 +00:00
Duncan Sands
46292be362 Revert commit 56835 since it breaks the build.
"If a re-materializable instruction has a register
operand, the spiller will change the register operand's
spill weight to HUGE_VAL to avoid it being spilled.
However, if the operand is already in the queue ready
to be spilled, avoid re-materializing it".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56837 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-30 10:00:30 +00:00
Evan Cheng
d41474d2c0 If a re-materializable instruction has a register operand, the spiller will change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56835 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-30 06:36:58 +00:00
Dale Johannesen
86b49f8e2d Next round of earlyclobber handling. Approach the
RA problem by expanding the live interval of an
earlyclobber def back one slot.  Remove
overlap-earlyclobber throughout.  Remove 
earlyclobber bits and their handling from
live internals.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56539 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-24 01:07:17 +00:00
Owen Anderson
134eb73fc3 Fetch the starting index of the block when assigning intervals. This gets live-in indices
correct in the presence of things like EH labels.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56410 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-21 20:43:24 +00:00
Dale Johannesen
fa48f94130 Remove AsmThatEarlyClobber etc. from LiveIntervalAnalysis
and redo as linked list walk.  Logic moved into RA.
Per review feedback.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56326 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-19 01:02:35 +00:00
Dale Johannesen
91aac1015e Add a bit to mark operands of asm's that conflict
with an earlyclobber operand elsewhere.  Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way 
that conflicts with an earlyclobber.  See also comments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56290 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 21:13:11 +00:00
Owen Anderson
99500aeb7c Live intervals for live-in registers should begin at the beginning of a basic block, not at the first
instruction.  Also, their valno's should have an unknown def.  This has no effect currently, but was
causing issues when StrongPHIElimination was enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56231 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-15 22:00:38 +00:00
Dan Gohman
014278e6a1 Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56189 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-13 17:58:21 +00:00
Owen Anderson
a41e47afc1 Allow the fast-path spilling code to attempt folding, but still leaving out remat and splitting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55012 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-19 22:12:11 +00:00
Owen Anderson
712c9f0690 The fast-path still needs to set kill markers and spill/restore points as appropriate.
With this patch, all of MultiSource/Applications and all of SPEC2000/2006 pass with
the SimpleSpiller and this fast-path enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55000 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-19 20:09:52 +00:00
Owen Anderson
ae339babb2 Add a flag to enable the fast spilling path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54958 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-19 00:17:30 +00:00
Owen Anderson
1719731d3d Fix a few more bugs:
1) Assign stack slots to new temporaries.
  2) Don't insert an interval into the return vector more than once.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54956 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-18 23:41:04 +00:00
Owen Anderson
9a03293145 Fix several bugs in the new fast-path:
1) Remove an incorrect assertion.
  2) Set the stack slot weight properly.
  3) Resize the VirtRegMap when needed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54949 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-18 21:20:32 +00:00