Commit Graph

1895 Commits

Author SHA1 Message Date
Chris Lattner
ec5a0b336a diaggroup categories should take precedence over diag-specific groups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104567 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 21:55:47 +00:00
Jakob Stoklund Olesen
09bc029865 Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 21:46:58 +00:00
Jakob Stoklund Olesen
73ea7bf450 Add the SubRegIndex TableGen class.
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 14:48:12 +00:00
Daniel Dunbar
54ddf3d9c7 tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104452 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 21:02:29 +00:00
Daniel Dunbar
4072886a69 tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor
it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104270 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:20:32 +00:00
Sean Hunt
853197557c Replace FIRST_* and LAST_* macros with a generic STMT_RANGE macro
Also rename ABSTRACT to ABSTRACT_STMT

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 06:22:50 +00:00
Evan Cheng
22c687b642 Added a QQQQ register file to model 4-consecutive Q registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 02:13:41 +00:00
Evan Cheng
dbf67fefea Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 23:55:47 +00:00
Chandler Carruth
93ca7b60bf Update tablegen to generate shorts instead of chars for subgroup arrays.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103704 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 07:43:47 +00:00
Dan Gohman
a6cb641f48 Add initial kill flag support to FastISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 23:54:07 +00:00
Douglas Gregor
7d9663c70b Fixes for Microsoft Visual Studio 2010, from Steven Watanabe!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103457 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 06:17:44 +00:00
Sean Callanan
1a8b789a4b Eliminated the classification of control registers into %ecr_
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:59:00 +00:00
Dan Gohman
34dcc6fadc Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:33:48 +00:00
Evan Cheng
b63387afc6 Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103172 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 06:36:08 +00:00
Sean Hunt
44ed2c31a5 Fix some stylistic issues with my last commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103164 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 05:24:38 +00:00
Shantonu Sen
d1dd5ed0ed Add newline to end of file to avoid warning
when building llvm with clang


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103084 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 13:56:46 +00:00
Sean Hunt
dc896a4118 Include the right header for toupper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103073 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 04:31:44 +00:00
Sean Hunt
84e2f959b7 Add an emitter to handle the list of clang statement nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103071 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 04:13:08 +00:00
Chris Lattner
af1465b17b add the ability to associate 'category' names with clang diagnostics
and diagnostic groups.  This allows the compiler to group 
diagnostics together (e.g. "Logic Warning", 
"Format String Warning", etc) like the static analyzer does.  
This is not exposed through anything in the compiler yet.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 20:44:23 +00:00
Daniel Dunbar
4f83e73a6d MC/Matcher: Add support for over-riding the default MatchInstruction function
name (for example, to allow targets to interpose the actual MatchInstruction
function).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 00:33:13 +00:00
Evan Cheng
b55c8bed9d Add a pseudo instruction REG_SEQUENCE that takes a list of registers and
sub-register indices and outputs a single super register which is formed from
a consecutive sequence of registers.

This is used as register allocation / coalescing aid and it is useful to
represent instructions that output register pairs / quads. For example,
v1024, v1025 = vload <address>
where v1024 and v1025 forms a register pair.

This really should be modelled as
v1024<3>, v1025<4> = vload <address>
but it would violate SSA property before register allocation is done.

Currently we use insert_subreg to form the super register:
v1026 = implicit_def
v1027 - insert_subreg v1026, v1024, 3
v1028 = insert_subreg v1027, v1025, 4
...
      = use v1024
      = use v1028

But this adds pseudo live interval overlap between v1024 and v1025.

We can now modeled it as
v1024, v1025 = vload <address>
v1026 = REG_SEQUENCE v1024, 3, v1025, 4
...
      = use v1024
      = use v1026

After coalescing, it will be
v1026<3>, v1025<4> = vload <address>
...
      = use v1026<3>
      = use v1026


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01 00:28:44 +00:00
Sean Callanan
a0f914b6c1 Fixes to edis that mark x86 call targets as
memory operands rather than immediate operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102217 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-23 22:17:17 +00:00
Johnny Chen
56a1afb6b0 When doing Thumb disassembly, there's no need to consider t2ADDrSPi12/t2SUBrSPi12,
as their generic counterparts t2ADDri12/t2SUBri12 should suffice.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101929 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 18:45:24 +00:00
Chris Lattner
acfb70f750 stop computing InstImpInputs, it is dead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101881 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 06:30:25 +00:00
Chris Lattner
62bcec82b2 DAGInstruction::ImpOperands is dead after my recent tblgen work, zap it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101880 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 06:28:43 +00:00
Anton Korobeynikov
928eb49cae Make processor FUs unique for given itinerary. This extends the limit of 32
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-18 20:31:01 +00:00
Dan Gohman
b35798347e Fix a bunch of namespace polution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101376 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 17:08:50 +00:00
Benjamin Kramer
be10811323 EDis: Don't include inttypes.h. We support compilers which don't provide it. It was unused anyways.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14 13:56:38 +00:00
Sean Callanan
9899f70a74 Fixed a nasty layering violation in the edis source
code.  It used to #include the enhanced disassembly
information for the targets it supported straight
out of lib/Target/{X86,ARM,...} but now it uses a
new interface provided by MCDisassembler, and (so
far) implemented by X86 and ARM.

Also removed hacky #define-controlled initialization
of targets in edis.  If clients only want edis to
initialize a limited set of targets, they can set
--enable-targets on the configure command line.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101179 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13 21:21:57 +00:00
Johnny Chen
1808e4d251 If all the bit positions are not specified; do not decode the instructions.
We are bound to fail!  For proper disassembly, the well-known encoding bits
of the instruction must be fully specified.

This also removes pseudo instructions from considerations of disassembly,
which is a better design and less fragile than the name matchings.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100899 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09 21:01:02 +00:00
Bob Wilson
ec80e2693a Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargets
such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100892 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09 20:41:18 +00:00
Johnny Chen
e0c74fb1de ARM decoder emitter should print out useful information unconditionally when it
encounters decoding conflicts, instead of wrapping it inside the DEBUG() macro. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100886 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09 19:31:33 +00:00
Johnny Chen
2d16a67b94 Now that Evan Cheng has fixed the coalescer bug (r100804), the workaround code
to avoid memcpy() call is no longer necessary.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100811 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 21:23:54 +00:00
Benjamin Kramer
454c4ce479 Various MSVC warning fixes about truncated 64 bit shifts and const pointers passed to free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100767 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 15:25:57 +00:00
Benjamin Kramer
127dc5e615 Use errs instead of fprintf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 09:42:29 +00:00
Sean Callanan
8f993b8c24 Added support for ARM disassembly to edis.
I also added a rule to the ARM target's Makefile to
build the ARM-specific instruction information table
for the enhanced disassembler.

I will add the test harness for all this stuff in
a separate commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100735 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 00:48:21 +00:00
Chris Lattner
75361b69f3 rename llvm::llvm_report_error -> llvm::report_fatal_error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100709 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 22:58:41 +00:00
Sean Callanan
5edca81626 Fixed a bug where the disassembler would allow an immediate
argument that had to be between 0 and 7 to have any value,
firing an assert later in the AsmPrinter.  Now, the
disassembler rejects instructions with out-of-range values
for that immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100694 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 21:42:19 +00:00
Eric Christopher
72666f2be9 Fix typo and correct comment somewhat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100691 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 20:58:16 +00:00
Johnny Chen
3c500e6947 Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call in
ARMDecoderEmitter.cpp, with FIXME comment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100690 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 20:53:12 +00:00
Anton Korobeynikov
96085a36db Initial support for different kinds of FU reservation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100645 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:19:32 +00:00
Jakob Stoklund Olesen
fddb7667ca Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.

This works well because TableGen resolves member references late:

class I : Instruction {
  AddrMode AM = AddrModeNone;
  let TSFlags{3-0} = AM.Value;
}

let AM = AddrMode4 in
def ADD : I;

TSFlags gets the expected bits from AddrMode4 in this example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-05 03:10:20 +00:00
Chris Lattner
35c33bd772 change a ton of code to not implicitly use the "O" raw_ostream
member of AsmPrinter.  Instead, pass it in explicitly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100306 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-04 04:47:45 +00:00
Chandler Carruth
1e86e3fb4b Fix a warning in GCC about a pointless typedef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100268 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-03 04:45:24 +00:00
Chandler Carruth
b421640efa Add the new ARMDecodeEmitter to CMake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100267 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-03 04:36:43 +00:00
Johnny Chen
55f71187a5 Move variable "Bits" declaration/definition into the DEBUG block where its usage
is expected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100247 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 23:13:52 +00:00
Johnny Chen
493a441391 Fixed build warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100244 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 22:51:04 +00:00
Johnny Chen
9981814a40 Change from .../Support/DataTypes.h to .../System/DataTypes.h.
(Fix build failure)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 22:41:06 +00:00
Johnny Chen
b68a3ee82a Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Reviewed by Chris Latter and Bob Wilson.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 22:27:38 +00:00
Chris Lattner
283d1ceb57 Switch pattern sorting predicate from stable sort -> sort, it
doesn't need to be stable because the patterns are fully ordered.

Add a first level sort predicate that orders patterns in this
order:  1) scalar integer operations 2) scalar floating point 
3) vector int 4) vector float.  This is a trivial sort on their
top level pattern type so it is nice and transitive.  The
benefit of doing this is that simple integer operations are
much more common than insane vector things and isel was trying
to match the big complex vector patterns before the simple
ones because the complexity of the vector operations was much
higher.  Since they can't both match, it is best (for compile
time) to try the simple integer ones first.

This cuts down the # failed match attempts on real code by
quite a bit, for example, this reduces backtracks on crafty
(as a random example) from 228285 -> 188369.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99797 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-29 02:02:45 +00:00
Chris Lattner
4810736134 revert 99795, as mentioned, it is disabled anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99796 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-29 01:58:15 +00:00
Chris Lattner
a0401249e8 Check in a (disabled) failed attempt to improve the ordering of
patterns within the generated matcher.  This works great except
that the sort fails because the relation defined isn't 
transitive.  I have a much simpler solution coming next, but want
to archive the code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99795 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-29 01:56:19 +00:00
Chris Lattner
48e86dbe29 print the complexity of the pattern being matched in the
comment in the generated table.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-29 01:40:38 +00:00
Chris Lattner
2a22cdc716 improve type checking of SDNode operand count. This rejects all cases
where an incorrect number of operands is provided to an sdnode instead
of just a few cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 08:48:47 +00:00
Chris Lattner
caa8870fe0 finally remove the immAllOnesV_bc/immAllZerosV_bc patterns
and those derived from them.  These are obnoxious because
they were written as: PatLeaf<(bitconvert).  Not having an
argument was foiling adding better type checking for operand
count matching up with what was required (in this case,
bitconvert always requires an operand!)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99759 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 08:43:23 +00:00
Chris Lattner
7a0eb91b4c teach tblgen to allow patterns like (add (i32 (bitconvert (i32 GPR))), 4),
transforming it into (add (i32 GPR), 4).  This allows us to write type
generic multi patterns and have tblgen automatically drop the bitconvert
in the case when the types align.  This allows us to fold an extra load
in the changed testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99756 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 08:38:32 +00:00
Chris Lattner
b775b1e20b validate that input sdnodes don't exist in an output pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 06:57:56 +00:00
Chris Lattner
c217305f76 eliminate a bunch of code duplication in ParseTreePattern
by rotating it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 06:50:34 +00:00
Chris Lattner
c812261221 SDTCisVT<0, isVoid> is not valid, reject it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99744 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 06:04:39 +00:00
Chris Lattner
aa4e3391c8 add an optimized form of OPC_EmitMergeInputChains for the 1, 0 and
1, 1 cases which are by-far the most frequent.  This shrinks the X86
isel table from 77014 -> 74657 bytes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99740 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 05:50:16 +00:00
Chris Lattner
b4a52b04bd fix a long standing fixme, which required fixing a bunch of other
issues to get here.  We now trim the result type list of the
CompleteMatch or MorphNodeTo operation to be the same size as the
thing we're matching.  this means that if you match (add GPR, GPR)
with an instruction that produces a normal result and a flag that
we now trim the result in tblgen instead of having to do it 
dynamically.  This exposed a bunch of inconsistencies in result
counting that happened to be getting lucky since the days of the
old isel.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99728 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 20:45:15 +00:00
Chris Lattner
0d7952ed5a fix CodeGenTarget::getRegisterVTs to not return the
same vt multiple times for a register.  For example,
ECX is in 5 different i32 reg classes, just return 
1 i32 instead of 5.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99727 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 20:32:26 +00:00
Chris Lattner
9414ae5291 hoist some funky logic into CodeGenInstruction
from two places in CodeGenDAGPatterns.cpp, and
use it in DAGISelMatcherGen.cpp instead of using
an incorrect predicate that happened to get lucky
on our current targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99726 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 20:09:24 +00:00
Chris Lattner
0be6fe7139 continue pushing tblgen's support for nodes with multiple
results forward.  We can now handle an instruction that 
produces one implicit def and one result instead of one or
the other when not at the root of the pattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99725 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 19:15:02 +00:00
Chris Lattner
5d3569e93c fix a bug in my recent patch that increased opcode size to 2 bytes:
the index comments nested under OPC_SwitchOpcode were off by one.
This fixes the comments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99722 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 18:49:33 +00:00
Dan Gohman
f65f294c99 Remove an unnecessary #include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99714 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 16:33:36 +00:00
Chris Lattner
310adf1c6f remove parallel support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99703 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 02:53:27 +00:00
Jakob Stoklund Olesen
70feca409e Teach TableGen to understand X.Y notation in the TSFlagsFields strings.
Remove much horribleness from X86InstrFormats as a result. Similar
simplifications are probably possible for other targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99539 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 18:52:01 +00:00
Chris Lattner
d5d5a3dcba Change tblgen to emit FOOISD opcode names as two
bytes instead of one byte.  This is important because
we're running up to too many opcodes to fit in a byte
and it is aggrevated by FIRST_TARGET_MEMORY_OPCODE
making the numbering sparse.  This just bites the
bullet and bloats out the table.  In practice, this
increases the size of the x86 isel table from 74.5K
to 76K.  I think we'll cope :)

This fixes rdar://7791648


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99494 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 06:33:05 +00:00
Jakob Stoklund Olesen
d1baa252c4 Fix evil TableGen bug in template parameters with defaults.
If a TableGen class has an initializer expression containing an X.Y subexpression,
AND X depends on template parameters,
AND those template parameters have defaults,
AND some parameters with defaults are beyond position 1,
THEN parts of the initializer expression are evaluated prematurely with the default values when the first explicit template parameter is substituted, before the remaining explicit template parameters have been substituted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99492 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 06:23:34 +00:00
Chris Lattner
084df627c8 add plumbing for handling multiple result nodes
in some more places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99366 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:41:19 +00:00
Chris Lattner
cc87830732 implement SDTCisVTSmallerThanOp with EnforceSmallerThan
instead of reimplementing it wrong and poorly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99357 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:06:46 +00:00
Chris Lattner
66fb9d26c6 bring sanity to EnforceVectorEltType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:01:16 +00:00
Chris Lattner
640a3f5309 Cleanup getImplicitType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99353 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 23:50:31 +00:00
Chris Lattner
9972aff7da reject void in intrinsic type lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99347 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 23:46:27 +00:00
Chris Lattner
93dc92e412 Change intrinsic result type for void to store it as an empty list
instead of as a single element list with VoidTy.  Now with a fix
for the verifier.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-22 20:56:36 +00:00
Daniel Dunbar
32f6a8b8bb Fix suggested parentheses warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99111 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-21 01:38:21 +00:00
Eric Christopher
d7de54068c Revert r99009 temporarily it seems to be breaking the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99011 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 23:04:23 +00:00
Chris Lattner
26e763753b Change intrinsic result type for void to store it as an empty list
instead of as a single element list with VoidTy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99009 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 22:40:56 +00:00
Chris Lattner
2e68a02c26 make getOperandNum a static function (since it's just used by
ApplyTypeConstraint) and make it handle multiple result nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99003 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 21:56:21 +00:00
Chris Lattner
d734919465 major surgery on tblgen: generalize TreePatternNode
to maintain a list of types (one for each result of
the node) instead of a single type.  There are liberal
hacks added to emulate the old behavior in various
situations, but they can start disolving now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98999 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 21:37:09 +00:00
Chris Lattner
774ce29399 make FillWithPossibleTypes take a predicate to filter types so that
we don't blow the smallvector as often.  No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98968 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 17:41:26 +00:00
Chris Lattner
1e50631675 resolve fixme: we now infer the instruction-level 'isvariadic' bit
from the pattern if present, and we use it instead of the bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 05:34:15 +00:00
Chris Lattner
e8cabf3c2e add a new SDNPVariadic SDNP node flag, and use it in
dag isel gen instead of instruction properties.  This
allows the oh-so-useful behavior of matching a variadic
non-root node.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98934 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 05:07:09 +00:00
Chris Lattner
5a9b8fb95c rewrite EnforceSmallerThan to be less bone headed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98933 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 04:54:36 +00:00
Daniel Dunbar
65f35d5703 Fix -Asserts warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98927 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 03:18:20 +00:00
Chris Lattner
aac5b5b2e5 eliminate the last use of EEVT::isUnknown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98918 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 01:14:27 +00:00
Chris Lattner
e14d2e210d Finally change the instruction looking map to be a densemap from
record* -> instrinfo instead of std::string -> instrinfo.

This speeds up tblgen on cellcpu from 7.28 -> 5.98s with a debug
build (20%).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98916 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 01:07:44 +00:00
Chris Lattner
6a91b18e57 make inst_begin/inst_end iterate over InstructionsByEnumValue.
Use CodeGenTarget::getInstNamespace in one place and fix it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 01:00:55 +00:00
Chris Lattner
01dcecc214 revert 98912
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98914 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:50:47 +00:00
Chris Lattner
a28bc686fa make inst_begin/inst_end iterate over InstructionsByEnumValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98912 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:40:22 +00:00
Chris Lattner
f65027842e change Target.getInstructionsByEnumValue to return a reference
to a vector that CGT stores instead of synthesizing it on every 
call.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98910 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:34:35 +00:00
Chris Lattner
e4e8bb1541 factor copy and paste code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98908 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:23:20 +00:00
Chris Lattner
b61e09de6d don't go through getInstructions().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98906 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:18:23 +00:00
Chris Lattner
f30187a363 look up instructions by record, not by name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:07:20 +00:00
Chris Lattner
928795387f expand tblgen's support for instructions with implicit defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98900 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 23:57:40 +00:00
Chris Lattner
6c6ba36493 infer results of a pattern from implicit defs. This allows you to do something
like this:

 def : Pat<(add ...),
           (FOOINST)>;

When fooinst only has a single implicit def (e.g. to R1).  This will be handled
as if written as (set R1, (FOOINST ...))



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 23:15:10 +00:00
Chris Lattner
f506b6b471 capture implicit uses and defs in CodeGenInstruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 21:42:03 +00:00
Chris Lattner
ef988984d7 simplify this code, the # of sets in the pattern for an instruction
shouldn't change this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98872 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 21:15:05 +00:00
Chris Lattner
0b6c926856 disallow concatenation of two dags with different operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98871 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 21:07:51 +00:00