Commit Graph

4091 Commits

Author SHA1 Message Date
Anton Korobeynikov
4d72860835 Model operand restrictions of mul-like instructions on ARMv5 via
earlyclobber stuff. This should fix PRs 2313 and 8157.

Unfortunately, no testcase, since it'd be dependent on register
assignments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122663 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-01 20:38:38 +00:00
NAKAMURA Takumi
7d63a2c2e8 CMake: Add disabling optimization on MSVC8 and MSVC10 as workaround for some files in Target/ARM and Target/X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122623 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-29 03:59:27 +00:00
Andrew Trick
2da8bc8a5f Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.

Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.

Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.

Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.

ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.

ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 05:03:26 +00:00
Andrew Trick
6e8f4c4048 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 04:28:06 +00:00
Jim Grosbach
f12eee75d1 Use a StringSwitch<> instead of a manually constructed string matcher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122530 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 00:03:39 +00:00
Jim Grosbach
b0ad9cf935 Remove dead patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122524 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23 23:20:13 +00:00
Jim Grosbach
940c8e5494 Recognize a few more documented register name aliases for ARM in the asm lexer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122523 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23 23:19:54 +00:00
Bob Wilson
3c904694fc Radar 8803471: Fix expansion of ARM BCCi64 pseudo instructions.
If the basic block containing the BCCi64 (or BCCZi64) instruction ends with
an unconditional branch, that branch needs to be deleted before appending
the expansion of the BCCi64 to the end of the block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122521 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23 22:45:49 +00:00
Chris Lattner
036609bd7d Flag -> Glue, the ongoing saga
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23 18:28:41 +00:00
Jim Grosbach
9584bd83e6 Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122456 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-22 23:26:02 +00:00
Bob Wilson
316009054e Add ARM-specific DAG combining to cast i64 vector element load/stores to f64.
Type legalization splits up i64 values into pairs of i32 values, which leads
to poor quality code when inserting or extracting i64 vector elements.
If the vector element is loaded or stored, it can be treated as an f64 value
and loaded or stored directly from a VPR register.  Use the pre-legalization
DAG combiner to cast those vector elements to f64 types so that the type
legalizer won't mess them up.  Radar 8755338.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122319 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21 06:43:19 +00:00
Eric Christopher
c19aadb8b0 Arm and thumb call instructions are also in different orders.
Fixes rdar://8782223


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122313 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21 03:50:43 +00:00
Chris Lattner
f1b4eafbfe rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
something that just glues two nodes together, even if it is
sometimes used for flags.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122310 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21 02:38:05 +00:00
Eric Christopher
6e90ce21cc If we're not using reg+reg offset we're using reg+imm, set the opcode
to be the one we want to use. bugpoint reduced testcase is a little large,
I'll see if I can simplify it down more.

Fixes part of rdar://8782207


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122307 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21 02:12:07 +00:00
Bill Wendling
a519d57725 Fix a copy-pasto. When the tBR_JTr instruction was converted to using the
tPseudoInst class, its size was changed from "special" to "2 bytes". This is
incorrect because the jump table will no longer be taken into account when
calculating branch offsets.
<rdar://problem/8782216>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122303 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21 01:57:15 +00:00
Bill Wendling
9a4d2e40a0 Comment cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122302 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21 01:54:40 +00:00
Rafael Espindola
1ec5bd31fe Remove the MCObjectFormat class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122147 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 05:37:28 +00:00
Rafael Espindola
bff66a86e6 Move some data to the TargetWriter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122134 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 03:27:34 +00:00
Bill Wendling
a68a4fdf37 r120333 changed the opcode for the Thumb1 stuff from ARM::tMOVr to
ARM::tMOVgpr2gpr. But this check didn't change. As a result, we were getting
misaligned references to the jump table from an ADR instruction.

There is a test case, but unfortunately it's sensitive to random code changes.

<rdar://problem/8782223>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122131 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 02:13:59 +00:00
Bill Wendling
cd080249fc RemoveUnusedCPEntries can change things. Track it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122129 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 01:53:06 +00:00
Bob Wilson
094dd80ecc Rearrange some Neon multiclasses. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 00:42:58 +00:00
Bob Wilson
3deb45149a Fix result type of Neon floating-point comparisons against zero.
The result vector elements are always integers.  Radar 8782191.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122112 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 00:04:33 +00:00
Bob Wilson
3a75b9bc8f Add some missing entries in ARMTargetLowering::getTargetNodeName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122111 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 00:04:26 +00:00
Bill Wendling
976ef86689 During local stack slot allocation, the materializeFrameBaseRegister function
may be called. If the entry block is empty, the insertion point iterator will be
the "end()" value. Calling ->getParent() on it (among others) causes problems.

Modify materializeFrameBaseRegister to take the machine basic block and insert
the frame base register at the beginning of that block. (It's very similar to
what the code does all ready. The only difference is that it will always insert
at the beginning of the entry block instead of after a previous materialization
of the frame base register. I doubt that that matters here.)

<rdar://problem/8782198>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122104 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 23:09:14 +00:00
Bob Wilson
9bb43e1675 Avoid report_fatal_error in ARM's PrintAsmOperand method.
The standard error handling in AsmPrinter::EmitInlineAsm handles this much
better, so just use it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122100 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 23:06:42 +00:00
Jim Grosbach
a3dbd3a244 If The ARM WriteNopData() gets an unaligned byte count to pad out, fill in with
a partial value. rdar://8782954

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122078 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 19:03:02 +00:00
Jim Grosbach
f0db261e97 Add bits 31-28 to the Thumb2 encoding of TBB/TBH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122076 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 18:42:56 +00:00
Jim Grosbach
6ec6eeb692 Handle 2 and 4 byte data blob fixup values for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122075 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 18:39:10 +00:00
Rafael Espindola
6024c97ffa Stub out explicit MCELFObjectTargetWriter interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 17:45:22 +00:00
Rafael Espindola
285b3e5b61 Move createELFObjectWriter to its own header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 16:59:53 +00:00
Daniel Dunbar
1139d5090a MC/ARM: Use aggressive symbol folding (important for jump tables, for example).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122044 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 06:00:24 +00:00
Daniel Dunbar
7b62afac0a MC/Target: Remove HasScatteredSymbols target hook variable, which has been
superceded and was effectively dead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122024 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 02:06:08 +00:00
Bob Wilson
a1f544b62e Use PairDRegs to implement ConcatVectors. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122017 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 01:21:08 +00:00
Jim Grosbach
3efad8fad4 Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121990 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 19:11:16 +00:00
Daniel Dunbar
5d05d9769e MC/Mach-O: Lift some MachObjectWriter arguments into the target specific
interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121981 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 17:21:02 +00:00
Daniel Dunbar
ae5abd595f MC/Mach-O: Stub out explicit MCMachObjectTargetWriter interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121973 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 16:09:19 +00:00
Daniel Dunbar
aa4b7dd13b MC/Mach-O: Move createMachObjectWriter into MCMachObjectWriter.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121971 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 16:08:33 +00:00
Daniel Dunbar
2761fc4270 MC: Move target specific fixup info descriptors to TargetAsmBackend instead of
the MCCodeEmitter, which seems like a better organization.
 - Also, cleaned up some magic constants while in the area.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121953 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 03:20:06 +00:00
Matt Beaumont-Gay
656b3d22f7 Delete an extra "Imm5 = ", caught by GCC's -Wsequence-point but not by Clang
(see PR4579).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121939 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 01:34:26 +00:00
Bill Wendling
6baf46dbea Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff for
it. I.e., it was always an immediate value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121932 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 00:50:33 +00:00
Bill Wendling
5a54516adf Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRi
respectively.

It may be a bug that these opcodes are getting this far into machine code
generation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121931 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 00:49:54 +00:00
Bill Wendling
dedec2b89d Add encodings for Thumb1 Spill and Restore pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121929 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 00:38:41 +00:00
Jim Grosbach
3e333637f1 Thumb1 had two patterns for the same load-from-constant-pool instruction.
Canonicalize on tLDRpci and remove tLDRcp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121920 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 23:52:36 +00:00
Eric Christopher
836c6245ad Don't handle -arm-long-calls in fast isel for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 23:47:29 +00:00
Bill Wendling
7a905a82f7 If we're changing the frame register to a physical register other than SP, we
need to use tLDRi and tSTRi instead of tLDRspi and tSTRspi respectively.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 23:32:27 +00:00
Bill Wendling
dc3813750e Whitespace cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121914 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 23:31:24 +00:00
Bob Wilson
0406356cd4 Add Neon VCVT instructions for f32 <-> f16 conversions.
Clang is now providing intrinsics for these and so we need to support them
in the backend.  Radar 8068427.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121902 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 22:14:12 +00:00
Jim Grosbach
d481110ef7 Tweak a few pseudo-inst pattern base classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 19:03:16 +00:00
Jim Grosbach
41b1d4e472 The new t2LEApcrel* pseudo instructions need the size specified.
rdar://8768390

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 18:48:45 +00:00
Owen Anderson
47dbd429da Implement cleanups suggested by Daniel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 18:48:27 +00:00