Commit Graph

9 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
d3bdf19ce7 Added support for fround, fextend and FP_TO_SINT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72483 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-27 17:23:44 +00:00
Evan Cheng
027fdbe3ba Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59953 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-24 07:34:46 +00:00
Bruno Cardoso Lopes
d3a680dda5 Added new features to represent specific instructions groups
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54213 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-30 17:01:06 +00:00
Bruno Cardoso Lopes
7728f7e890 Fixed features usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53277 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-09 05:32:22 +00:00
Bruno Cardoso Lopes
225ca9cdd7 Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
  yet, but they allow the future inclusion of features easier. Among new features,
  we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
  integer
  and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
  aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
  sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
  FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
  FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
  return copy, no homing location within EABI, non 32-bit stack objects
  arguments, and asm constraint for float.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
Chris Lattner
4ee451de36 Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 20:36:04 +00:00
Bruno Cardoso Lopes
000604afd4 Better processor definition
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43749 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-06 03:15:20 +00:00
Bruno Cardoso Lopes
6d32ca0762 support for Schedule included on Mips.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41159 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-18 02:18:07 +00:00
Bruno Cardoso Lopes
972f5896e4 Initial Mips support, here we go! =)
- Modifications from the last patch included
  (issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37461 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-06 07:42:06 +00:00