Evan Cheng
cae6a12a99
NEON scheduling info fix. vmov reg, reg are single cycle instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 20:50:58 +00:00
Evan Cheng
0e55fd61ae
ARM instruction itinerary fixes:
...
1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115121 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 01:08:25 +00:00
Evan Cheng
3881cb7a5d
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP
...
pipeline forwarding path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 22:42:35 +00:00
Evan Cheng
5d42c567c9
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115010 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 00:49:25 +00:00
Evan Cheng
7e1bf305cf
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115008 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 00:27:46 +00:00
Evan Cheng
63d66eed16
Add support to model pipeline bypass / forwarding.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115005 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 23:50:49 +00:00
Evan Cheng
27fdcd1c95
Remove a unused instruction itinerary class.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114782 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-25 01:06:02 +00:00
Evan Cheng
576a3968a2
Fix zero and sign extension instructions scheduling itineraries.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114780 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-25 00:49:35 +00:00
Evan Cheng
bd30ce4311
More pseudo instruction scheduling itinerary fixes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114768 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24 22:41:41 +00:00
Evan Cheng
5be3922321
Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114766 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24 22:03:46 +00:00
Evan Cheng
5f54ce3473
For each instruction itinerary class, specify the number of micro-ops each
...
instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.
This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 18:18:55 +00:00
Evan Cheng
7602acbf3b
Fix LDM_RET schedule itinery.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 22:57:08 +00:00
Anton Korobeynikov
928eb49cae
Make processor FUs unique for given itinerary. This extends the limit of 32
...
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-18 20:31:01 +00:00
Anton Korobeynikov
e1676011c6
Split A8/A9 itins - they already were too big.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100672 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:22:11 +00:00
Anton Korobeynikov
0a3e2b591c
Fix itins for VABA
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100657 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:20:42 +00:00
Anton Korobeynikov
f8b5c63617
VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:20:13 +00:00
Anton Korobeynikov
a31c6fb65e
Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :(
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100650 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:20:02 +00:00
Anton Korobeynikov
c492e09455
Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100647 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:19:46 +00:00
Anton Korobeynikov
391b3431e2
Make use of new reserved/required scheduling stuff: introduce VFP and NEON locks to model domain cross stalls precisly.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100646 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:19:40 +00:00
David Goodwin
658ea60997
Finish scheduling itineraries for NEON.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82788 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 18:38:29 +00:00
David Goodwin
1f52895692
Make the end-of-itinerary mark explicit. Some cleanup.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82709 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24 20:22:50 +00:00
David Goodwin
127221fbdc
Checkpoint NEON scheduling itineraries.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82657 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-23 21:38:08 +00:00
David Goodwin
b2bb7db9e2
Add Cortex-A8 VFP model.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82483 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-21 20:52:17 +00:00
David Goodwin
5d598aaf3d
Update Cortex-A8 instruction itineraries for integer instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79436 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-19 18:00:44 +00:00
Evan Cheng
bc9b754091
Turn on if-conversion for thumb2.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79084 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15 07:59:10 +00:00
David Goodwin
6d3d9c3fc3
Finalize itineraries for cortex-a8 integer multiply
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78908 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-13 15:51:13 +00:00
David Goodwin
546952fd60
Allow a zero cycle stage to reserve/require a FU without advancing the cycle counter.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78736 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 22:38:43 +00:00
David Goodwin
bcf81629b8
Checkpoint scheduling itinerary changes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78564 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 15:56:13 +00:00
Evan Cheng
6762d91c05
Add fake v7 itineraries for now.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76612 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-21 18:54:14 +00:00
Evan Cheng
8557c2bcb8
Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73747 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 01:51:50 +00:00