Commit Graph

93470 Commits

Author SHA1 Message Date
Ulrich Weigand
329d413199 [PowerPC] Add some FIXMEs
A bunch of extendend mnemomics ought to support '.' forms.
Add FIXMEs to the test case for those.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184757 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 17:00:22 +00:00
Aaron Watry
6c4b8fe9dd R600: Fix spelling error in comment
our -> or

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184756 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 16:57:57 +00:00
Ulrich Weigand
2e8bd89503 [PowerPC] Add predicted forms of branches
This adds support for the predicted forms of branches (+/-).
There are three cases to consider:
- Branches using a PPC::Predicate code
  For these, I've added new PPC::Predicate codes corresponding
  to the BO values for predicted branch forms, and updated insn
  printing to print them correctly.  I've also added new aliases
  for the asm parser matching the new forms.
- bt/bf
  I've added new aliases matching to gBC etc.
- bd(n)z variants
  I've added new instruction patterns for the predicted forms.

In all cases, the new patterns are used for the asm parser only.
(The new infrastructure ought to be sufficient to allow use by
the compiler too at some point.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184754 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 16:52:04 +00:00
NAKAMURA Takumi
a6a3fd6415 Move llvm/test/DebugInfo/arguments.ll to X86, for now. It is still Windows' PECOFF incompatible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184750 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 16:05:21 +00:00
Nadav Rotem
f4b0e81085 Rename the variable to fix a warning. Thanks Andy Gibbs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184749 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 15:59:47 +00:00
Reid Kleckner
dfad9e314e Look for Python 2 before Python 3 in CMakeLists.txt
All of LLVM's Python scripts only support Python 2 for widely understood
reasons.

Patch by Yonggang Luo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184732 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 13:21:16 +00:00
NAKAMURA Takumi
e7a939e1d8 llvm/test/CodeGen/X86: Add explicit -mtriple=x86_64-unknown-unknown.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184731 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 13:19:59 +00:00
NAKAMURA Takumi
4a931eb4c0 llvm/test/CodeGen/X86/legalize-shift-64.ll: Add explicit -mtriple=i686-unknown-unknown.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184730 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 13:19:52 +00:00
NAKAMURA Takumi
fb2c145498 llvm/test/DebugInfo/arguments.ll: Add explicit -mtriple=x86_64-unknown-unknown.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184729 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 13:19:47 +00:00
NAKAMURA Takumi
f1505ff35b NVPTXTargetObjectFile.h: Initialize some pointers as NULL in the constructor of NVPTXTargetObjectFile. ~NVPTXTargetObjectFile() tries to delete them.
It caused crash on some hosts since r184595.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184728 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 13:19:41 +00:00
Ulrich Weigand
48473a8de5 [PowerPC] Add t/f branch mnemonics to asm parser
This adds the bt/bf/bd(n)zt/bd(n)zf mnemonics as aliases for the
asm parser, resolving to the generic conditional patterns.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184725 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 12:49:20 +00:00
Arnold Schwaighofer
bc7c58d2b1 Reapply 184685 after the SetVector iteration order fix.
This should hopefully have fixed the stage2/stage3 miscompare on the dragonegg
testers.

"LoopVectorize: Use the dependence test utility class

We now no longer need alias analysis - the cases that alias analysis would
handle are now handled as accesses with a large dependence distance.

We can now vectorize loops with simple constant dependence distances.

  for (i = 8; i < 256; ++i) {
    a[i] = a[i+4] * a[i+8];
  }

  for (i = 8; i < 256; ++i) {
    a[i] = a[i-4] * a[i-8];
  }

We would be able to vectorize about 200 more loops (in many cases the cost model
instructs us no to) in the test suite now. Results on x86-64 are a wash.

I have seen one degradation in ammp. Interestingly, the function in which we
now vectorize a loop is never executed so we probably see some instruction
cache effects. There is a 2% improvement in h264ref. There is one or the other
TSCV loop kernel that speeds up.

radar://13681598"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184724 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 12:09:15 +00:00
Arnold Schwaighofer
7e96b4dfce LoopVectorize: Use SetVector for the access set
We are creating the runtime checks using this set so we need a deterministic
iteration order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184723 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 12:09:12 +00:00
Ulrich Weigand
e5a30f0ca2 [PowerPC] Support generic conditional branches in asm parser
This adds instruction patterns to cover the generic forms of
the conditional branch instructions.  This allows the assembler
to support the generic mnemonics.

The compiler will still generate the various specific forms
of the instruction that were already supported.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184722 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 11:55:21 +00:00
Ulrich Weigand
9679c47a07 [PowerPC] Support absolute branches
There is currently only limited support for the "absolute" variants
of branch instructions.  This patch adds support for the absolute
variants of all branches that are currently otherwise supported.

This requires adding new fixup types so that the correct variant
of relocation type can be selected by the object writer.

While the compiler will continue to usually choose the relative
branch variants, this will allow the asm parser to fully support
the absolute branches, with either immediate (numerical) or
symbolic target addresses.

No change in code generation intended.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184721 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 11:03:33 +00:00
Ulrich Weigand
9068d5310c [PowerPC] Support bd(n)zl and bd(n)zlrl
This adds support for the bd(n)zl and bd(n)zlrl instructions.
The patterns are currently used for the asm parser only.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184720 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 11:02:38 +00:00
Ulrich Weigand
813942a0cf [PowerPC] Support b(cond)l in the asm parser
This patch adds support for the conditional variants of bl.
The pattern is currently used by the asm parser only.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184719 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 11:02:19 +00:00
Ulrich Weigand
7e66f5c1b4 [PowerPC] Support blrl and variants in the asm parser
This patch adds support for blrl and its conditional variants.
The patterns are (currently) used for the asm parser only.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184718 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 11:01:55 +00:00
Vladimir Medic
90b1086b93 This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184716 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 10:05:34 +00:00
Michael Gottesman
567a1126fb [APFloat] Removed trailing whitespace from unittests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184715 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 09:58:09 +00:00
Michael Gottesman
683069ffba [APFloat] Added a large unittest for APFloat.add that checks that special values are computed correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184714 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 09:58:07 +00:00
Michael Gottesman
575694b6a7 [APFloat] Added support for parsing float strings which contain {inf,-inf,NaN,-NaN}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184713 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 09:58:05 +00:00
Michael Gottesman
fdec0c7a73 [APFloat] Added make{Zero,Inf} methods and implemented get{Zero,Inf} on top of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184712 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 09:58:02 +00:00
Michael Gottesman
fb25071a18 [APFloat] Removed a assert from significandParts() which says that one can only access the significand of FiniteNonZero/NaN floats.
The method significandParts() is a helper method meant to ease access to
APFloat's significand by allowing the user to not need to be aware of whether or
not the APFloat is using memory allocated in the instance itself or in an
external array.

This assert says that one can only access the significand of FiniteNonZero/NaN
floats. This makes it cumbersome and more importantly dangerous when one wishes
to zero out the significand of a zero/infinity value since one will have to deal
with the aforementioned quandary related to how the memory in APFloat is
allocated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184711 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 09:57:59 +00:00
Michael Gottesman
c29f5dc29e [APFloat] Rename macro convolve => PackCategoriesIntoKey so that it is clear what APFloat is actually using said macro for.
In the context of APFloat, seeing a macro called convolve suggests that APFloat
is using said value in some sort of convolution somewhere in the source code.
This is misleading.

I also added a documentation comment to the macro.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184710 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 09:57:57 +00:00
Andrew Trick
37d002f0a8 Add -mcpu to some unit tests that only fail on certain hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184709 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 09:51:30 +00:00
Amaury de la Vieuville
ebc3938ae7 ARM: check predicate bits for thumb instructions
When encoded to thumb, VFP instruction and VMOV/VDUP between scalar and
core registers, must have their predicate bit to 0b1110.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184707 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 09:15:01 +00:00
Amaury de la Vieuville
07c3e159d8 ARM: rGPR is meant to be unpredictable, not undefined
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184706 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 09:14:54 +00:00
Andrew Trick
98a9b72e8c Temporarily enable MI-Sched on X86.
Sorry for the unit test churn. I'll try to make the change permanently
next time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184705 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 09:13:20 +00:00
Amaury de la Vieuville
4ee72398a1 ARM: fix thumb1 nop decoding
In thumb1, NOP is a pseudo-instruction equivalent to mov r8, r8.
However the disassembler should not use this alias.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184703 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 09:11:53 +00:00
Amaury de la Vieuville
ff08da15cf ARM: fix IT decoding
mask == 0 -> UNPRED

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184702 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 09:11:45 +00:00
Amaury de la Vieuville
0c9f0c047d ARM: enable decoding of pc-relative PLD/PLI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184701 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 09:11:38 +00:00
Chandler Carruth
6bf3a05235 Add a flag to defer vectorization into a phase after the inliner and its
CGSCC pass manager. This should insulate the inlining decisions from the
vectorization decisions, however it may have both compile time and code
size problems so it is just an experimental option right now.

Adding this based on a discussion with Arnold and it seems at least
worth having this flag for us to both run some experiments to see if
this strategy is workable. It may solve some of the regressions seen
with the loop vectorizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184698 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 07:21:47 +00:00
Chandler Carruth
d77a0ca493 Filter out dragonegg when checked out into a projects subdirectory.
There is some hope of eventually supporting a unified build with it, but
until then this lets me (and others) check it out in this location
without things breaking.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184697 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 07:21:35 +00:00
David Blaikie
b26da887d6 DebugInfo: enumerator values returned as int64 as they are stored
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184694 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 07:11:08 +00:00
David Blaikie
20af501d6f DebugInfo: add some testing from an overly broad end-to-end test in Clang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184692 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 06:47:22 +00:00
Arnold Schwaighofer
ec677e2a64 Revert "LoopVectorize: Use the dependence test utility class"
This reverts commit cbfa1ca993.

We are seeing a stage2 and stage3 miscompare on some dragonegg bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184690 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 06:10:41 +00:00
Michael Gottesman
daee0b0def [APFloat] Removed out of date comment from isNormal().
I already finished the isIEEENormal => isNormal transition. So isNormal is now
IEEE-754R compliant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184687 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 04:19:37 +00:00
Michael Gottesman
db045ab153 [APFloat] Rename llvm::exponent_t => llvm::APFloat::ExponentType.
exponent_t is only used internally in APFloat and no exponent_t values are
exposed via the APFloat API. In light of such conditions it does not make any
sense to gum up the llvm namespace with said type. Plus it makes it clearer that
exponent_t is associated with APFloat.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184686 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 04:06:23 +00:00
Arnold Schwaighofer
cbfa1ca993 LoopVectorize: Use the dependence test utility class
We now no longer need alias analysis - the cases that alias analysis would
handle are now handled as accesses with a large dependence distance.

We can now vectorize loops with simple constant dependence distances.

  for (i = 8; i < 256; ++i) {
    a[i] = a[i+4] * a[i+8];
  }

  for (i = 8; i < 256; ++i) {
    a[i] = a[i-4] * a[i-8];
  }

We would be able to vectorize about 200 more loops (in many cases the cost model
instructs us no to) in the test suite now. Results on x86-64 are a wash.

I have seen one degradation in ammp. Interestingly, the function in which we
now vectorize a loop is never executed so we probably see some instruction
cache effects. There is a 2% improvement in h264ref. There is one or the other
TSCV loop kernel that speeds up.

radar://13681598

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184685 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 03:55:48 +00:00
Arnold Schwaighofer
5df684a6d1 LoopVectorize: Add utility class for checking dependency among accesses
This class checks dependences by subtracting two Scalar Evolution access
functions allowing us to catch very simple linear dependences.

The checker assumes source order in determining whether vectorization is safe.
We currently don't reorder accesses.
Positive true dependencies need to be a multiple of VF otherwise we impede
store-load forwarding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184684 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 03:55:45 +00:00
Arnold Schwaighofer
5737d3f433 LoopVectorize: Add utility class for building sets of dependent accesses
Sets of dependent accesses are built by unioning sets based on underlying
objects. This class will be used by the upcoming dependence checker.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184683 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 03:55:44 +00:00
Nadav Rotem
25961b469a SLP Vectorizer: Add support for vectorizing parts of the tree.
Untill now we detected the vectorizable tree and evaluated the cost of the
entire tree.  With this patch we can decide to trim-out branches of the tree
that are not profitable to vectorizer.

Also, increase the max depth from 6 to 12. In the worse possible case where all
of the code is made of diamond-shaped graph this can bring the cost to 2**10,
but diamonds are not very common.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184681 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 02:52:43 +00:00
Andrew Trick
f7b5e01636 Fix tail merging to assign the (more) correct BasicBlock when splitting.
This makes it possible to write unit tests that are less susceptible
to minor code motion, particularly copy placement. block-placement.ll
covers this case with -pre-RA-sched=source which will soon be
default. One incorrectly named block is already fixed, but without
this fix, enabling new coalescing and scheduling would cause more
failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184680 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 01:55:01 +00:00
Nadav Rotem
722b0a4d29 SLP Vectorizer: Fix a bug in the code that does CSE on the generated gather sequences.
Make sure that we don't replace and RAUW two sequences if one does not dominate the other.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184674 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-23 21:57:27 +00:00
Nadav Rotem
787ad64b98 SLP Vectorizer: Erase instructions outside the vectorizeTree method.
The RAII builder location guard is saving a reference to instructions, so we can't erase instructions during vectorization.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184671 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-23 19:38:56 +00:00
David Blaikie
fe2e66a6da DebugInfo: PR14404: Avoid truncating 64 bit values into 32 bits for ULEB128/SLEB128 generation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184669 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-23 18:31:11 +00:00
Tim Northover
7130a95617 AArch64: fix overzealous NEXTing for Windows testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184667 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-23 15:32:01 +00:00
Andrew Trick
0f2eec65fb Add MI-Sched support for x86 macro fusion.
This is an awful implementation of the target hook. But we don't have
abstractions yet for common machine ops, and I don't see any quick way
to make it table-driven.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184664 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-23 09:00:28 +00:00
Nadav Rotem
6959f08f44 SLP Vectorizer: Implement a simple CSE optimization for the gather sequences.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184660 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-23 06:15:46 +00:00