Commit Graph

2956 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
dbd4fe2b0a - Register v16i16 as valid VR256 register class
- Add more bitcasts for v16i16
- Since 135661 and 135662 already added the splat logic,
just add one more splat test for v16i16

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135663 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 02:24:08 +00:00
Bruno Cardoso Lopes
65b74e1d00 Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:

Instead of:
  vextractf128  $0, %ymm0, %xmm0
  punpcklbw %xmm0, %xmm0
  punpckhbw %xmm0, %xmm0
  vinsertf128 $0, %xmm0, %ymm0, %ymm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  vextractf128  $1, %ymm0, %xmm1
  shufps  $1, %xmm1, %xmm1
  movss %xmm1, 28(%rsp)
  movss %xmm1, 24(%rsp)
  movss %xmm1, 20(%rsp)
  movss %xmm1, 16(%rsp)
  vextractf128  $0, %ymm0, %xmm0
  shufps  $1, %xmm0, %xmm0
  movss %xmm0, 12(%rsp)
  movss %xmm0, 8(%rsp)
  movss %xmm0, 4(%rsp)
  movss %xmm0, (%rsp)
  vmovaps (%rsp), %ymm0
We get:
  vextractf128  $0, %ymm0, %xmm0
  punpcklbw %xmm0, %xmm0
  punpckhbw %xmm0, %xmm0
  vinsertf128 $0, %xmm0, %ymm0, %ymm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  vpermilps $85, %ymm0, %ymm0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:55:47 +00:00
Devang Patel
4ec14b0dee While emitting constant value, look through derived type and use underlying basic type to determine size and signness of the constant value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135627 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 21:57:04 +00:00
Eli Friedman
0381c21d2d PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135595 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 18:14:33 +00:00
Eric Christopher
03c45f60f3 New pointer rotate test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135562 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 03:09:11 +00:00
Evan Cheng
70955c2d12 Fix an obvious typo that's preventing x86 (32-bit) from using .literal16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135535 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 23:14:32 +00:00
Devang Patel
497a397f3e Revert r135423.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135454 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 00:28:24 +00:00
Devang Patel
1360bc8eb0 During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases.
[take 2]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135423 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18 20:55:23 +00:00
Bruno Cardoso Lopes
3aaa010ece Add AVX 128-bit sqrt versions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135404 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18 17:51:40 +00:00
Nick Lewycky
b8c129ea66 Delete empty unused file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135379 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18 05:54:06 +00:00
Bruno Cardoso Lopes
4201ecae92 Add AVX 128-bit patterns for sint_to_fp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135332 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-16 00:50:20 +00:00
Bruno Cardoso Lopes
5bc37dd131 Fix a couple of things:
1) Make non-legal 256-bit loads to be promoted to v4i64. This lets us
canonize the loads and handle things the same way we use to handle
for 128-bit registers. Despite of what one of the removed comments
explained, the load promotion would not mess with VPERM, it's only a
matter of doing the appropriate bitcasts when this instructions comes
to be introduced. Also make LOAD v8i32 legal.

2) Doing 1) exposed two bugs:
- v4i64 was being promoted to itself for several opcodes (introduced
in r124447 by David Greene) causing endless recursion and the stack to
explode.
- there was no support for allOnes BUILD_VECTORs and ANDNP would fail to
match because it was generating early target constant pools during
lowering.

3) The testcases are already checked-in, doing 1) exposed the
bugs in the current testcases.

4) Tidy up code to be more clear and explicit about AVX.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135313 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-15 22:24:33 +00:00
Eric Christopher
5427edeb68 Check register class matching instead of width of type matching
when determining validity of matching constraint. Allow i1
types access to the GR8 reg class for x86.

Fixes PR10352 and rdar://9777108

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135180 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 20:13:52 +00:00
Bruno Cardoso Lopes
62f67f86fe Add 256-bit load/store recognition and matching in several places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 18:50:58 +00:00
Benjamin Kramer
3ff25514ce Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135126 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 01:38:42 +00:00
Bruno Cardoso Lopes
53c95880f0 We already support 256-bit packed ADD, SUB, DIV, MUL. Add testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:28:55 +00:00
Bruno Cardoso Lopes
466b022c99 Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more
general version of X86ISD::ANDNP also opened the room for a little bit
of refactoring.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135088 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 21:36:51 +00:00
Eli Friedman
2a01946de4 Make sure we don't combine a large displacement and a frame index in the same addressing mode on x86-64. It can overflow, leading to a crash/miscompile.
<rdar://problem/9763308>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135084 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 21:29:53 +00:00
Bruno Cardoso Lopes
61905f0139 AVX Codegen support for 256-bit versions of vandps, vandpd, vorps, vorpd, vxorps, vxorpd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 01:15:33 +00:00
Chris Lattner
1afcace3a3 Land the long talked about "type system rewrite" patch. This
patch brings numerous advantages to LLVM.  One way to look at it
is through diffstat:
 109 files changed, 3005 insertions(+), 5906 deletions(-)

Removing almost 3K lines of code is a good thing.  Other advantages
include:

1. Value::getType() is a simple load that can be CSE'd, not a mutating
   union-find operation.
2. Types a uniqued and never move once created, defining away PATypeHolder.
3. Structs can be "named" now, and their name is part of the identity that
   uniques them.  This means that the compiler doesn't merge them structurally
   which makes the IR much less confusing.
4. Now that there is no way to get a cycle in a type graph without a named
   struct type, "upreferences" go away.
5. Type refinement is completely gone, which should make LTO much MUCH faster
   in some common cases with C++ code.
6. Types are now generally immutable, so we can use "Type *" instead 
   "const Type *" everywhere.

Downsides of this patch are that it removes some functions from the C API,
so people using those will have to upgrade to (not yet added) new API.  
"LLVM 3.0" is the right time to do this.

There are still some cleanups pending after this, this patch is large enough
as-is.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134829 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 17:41:24 +00:00
Chris Lattner
5445ecdf69 more tests not making the jump into the brave new world.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134820 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 16:57:10 +00:00
NAKAMURA Takumi
9eb36758ac test/CodeGen/X86/vector.ll: Tweak temporary output to appease Win32 hosts.
With Lit (not bash) in a test, multiple redirects >%t might open(%t, "w") multiple. It can be avoided if latter redirect is >>%t.

It might work even if ">/dev/null" were used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 10:22:28 +00:00
Jakob Stoklund Olesen
56573cc1ae Hoist spills within a basic block.
Try to move spills as early as possible in their basic block. This can
help eliminate interferences by shortening the live range being
spilled.

This fixes PR10221.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134776 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 00:25:03 +00:00
Evan Cheng
f0b3c12919 Fix broken x86_64 tests which specify non-64-bit cpu's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134756 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 22:29:33 +00:00
Eli Friedman
f06ff4eae3 Default 64-bit target features and SSE2 on when a triple specifies x86-64. Clean up all the other hacks which are now unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134753 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 22:16:47 +00:00
Julien Lerouge
f29608267b Add _allrem, _aullrem and _allmul to the runtime for MSVC.
http://llvm.org/bugs/show_bug.cgi?id=10305


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134744 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 21:40:25 +00:00
Cameron Zwarich
33390848a7 Add an intrinsic and codegen support for fused multiply-accumulate. The intent
is to use this for architectures that have a native FMA instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134742 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 21:39:21 +00:00
Jakob Stoklund Olesen
51458ed09e Be more aggressive about following hints.
RAGreedy::tryAssign will now evict interference from the preferred
register even when another register is free.

To support this, add the EvictionCost struct that counts how many hints
are broken by an eviction. We don't want to break one hint just to
satisfy another.

Rename canEvict to shouldEvict, and add the first bit of eviction policy
that doesn't depend on spill weights: Always make room in the preferred
register as long as the evictees can be split and aren't already
assigned to their preferred register.

Also make the CSR avoidance more accurate. When looking for a cheaper
register it is OK to use a new volatile register. Only CSR aliases that
have never been used before should be avoided.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134735 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 20:46:18 +00:00
Benjamin Kramer
9c64030445 Emit a more efficient magic number multiplication for exact sdivs.
We have to do this in DAGBuilder instead of DAGCombiner, because the exact bit is lost after building.

  struct foo { char x[24]; };
  long bar(struct foo *a, struct foo *b) { return a-b; }
is now compiled into
  movl	4(%esp), %eax
  subl	8(%esp), %eax
  sarl	$3, %eax
  imull	$-1431655765, %eax, %eax
instead of
  movl	4(%esp), %eax
  subl	8(%esp), %eax
  movl	$715827883, %ecx
  imull	%ecx
  movl	%edx, %eax
  shrl	$31, %eax
  sarl	$2, %edx
  addl	%eax, %edx
  movl	%edx, %eax

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134695 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 10:31:30 +00:00
Jakob Stoklund Olesen
caab27963b Remove a test that no longer makes sense.
It was testing a linear scan feature:

  Test if linearscan is unfavoring registers for allocation to allow
  more reuse of reloads from stack slots.

The greedy register allocator doesn't access any stack slots in this
function, so the linear scan feature was not being tested.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134666 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 00:24:03 +00:00
Nick Lewycky
9bf45d0b1a Let the inline asm 'q' constraint match float, and on 64-bit double too.
Fixes PR9602!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134665 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 00:19:27 +00:00
Eric Christopher
77ed1353bf Go ahead and emit the barrier on x86-64 even without sse2. The
processor supports it just fine.

Fixes PR9675 and rdar://9740801


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134664 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 00:04:56 +00:00
Eric Christopher
31b5f00c4e Add support for the X86 'l' constraint.
Fixes PR10149 and rdar://9738585

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134648 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 22:29:07 +00:00
Evan Cheng
18fb1d35db Add Mode64Bit feature and sink it down to MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134641 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 21:06:52 +00:00
Dan Gohman
211f53aa04 Revert r134366 and add an explicit triple to make this test host-independent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134447 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-05 22:09:19 +00:00
Jakob Stoklund Olesen
9693d4c3f0 Fix PR10277.
Remat during spilling triggers dead code elimination. If a phi-def
becomes unused, that may also cause live ranges to split into separate
connected components.

This type of splitting is different from normal live range splitting. In
particular, there may not be a common original interval.

When the split range is its own original, make sure that the new
siblings are also their own originals. The range being split cannot be
used as an original since it doesn't cover the new siblings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134413 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-05 15:38:41 +00:00
NAKAMURA Takumi
7495ea7fe9 test/CodeGen/X86/lsr-nonaffine.ll: Relax expressions for Win64 CC to appease Win32 hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134366 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-03 09:26:14 +00:00
Chandler Carruth
a42e665442 FileCheck-ize another X86 test, making it more precisely verify the
desired result based on the comments in the file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134354 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:43:16 +00:00
Chandler Carruth
432a8931e4 FileCheck-ize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134351 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:43:08 +00:00
Chandler Carruth
327b8f1706 FileCheck-ize and tighten up assertions to only check the relevant sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134350 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:43:04 +00:00
Chandler Carruth
44f52f2d39 FileCheck-ize and cleanup IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134349 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:43:01 +00:00
Chandler Carruth
b3ce947ecf FileCheck-ize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134348 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:59 +00:00
Chandler Carruth
f2a3b35a7c Remove a grep that is already checked with FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134346 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:56 +00:00
Chandler Carruth
3bd210ea8f FileCheck-ize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134345 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:53 +00:00
Chandler Carruth
45177cb85c FileCheck-ize and modernize IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:50 +00:00
Chandler Carruth
36da1d9633 FileCheck-ize and simplify RUNs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134343 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:48 +00:00
Chandler Carruth
431d63b560 FileCheck-ize and modernize the RUN line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134342 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:44 +00:00
Chandler Carruth
03119ab3d7 FileCheck-ize, tightening checks and avoiding a temporary file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134341 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:42 +00:00
Chandler Carruth
5a26013390 FileCheck-ize, tightening checks and avoiding a temporary file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134340 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:39 +00:00
Chandler Carruth
2fa43a7315 FileCheck-ize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:36 +00:00