Commit Graph

12513 Commits

Author SHA1 Message Date
Bob Wilson
916ac5b069 Add a comment to describe letters used in multiclass name suffixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83257 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-03 04:44:16 +00:00
Bob Wilson
8f07b9e8a9 Fix encoding problem for VMLS instruction.
Thanks to Johnny Chen for pointing this out!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83256 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-03 04:41:21 +00:00
Evan Cheng
048e36f536 getFunctionAlignment should return log2 alignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83242 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-02 06:57:25 +00:00
Evan Cheng
892597943a Forgot about ARM::tPUSH. It also has a new writeback operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83237 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-02 05:03:07 +00:00
Evan Cheng
62a1b5db44 Move load / store multiple before post-alloc scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83236 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-02 04:57:15 +00:00
David Goodwin
9843a93e83 Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83218 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 22:19:57 +00:00
David Goodwin
471850ab84 Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83215 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 21:46:35 +00:00
Evan Cheng
10469f8e48 ARM::tPOP and tPOP_RET each has an extra writeback operand now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83214 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 20:54:53 +00:00
Evan Cheng
0d92f5f768 Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
ld / st pairs, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83197 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 08:22:27 +00:00
Evan Cheng
7c043d7319 Update ARM JIT emitter to account for ld/st multiple changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83192 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 01:39:21 +00:00
Evan Cheng
d20d658675 Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83191 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 01:33:39 +00:00
Devang Patel
b0fdedb3fd Use MachineInstr as an processDebugLoc() argument.
This will allow processDebugLoc() to handle scopes for DWARF debug info. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83183 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30 23:12:50 +00:00
Bob Wilson
29e066965f Use OutStreamer.SwitchSection instead of writing out textual section directives.
Add a new TargetLoweringObjectFileMachO::getConstTextCoalSection method to
get access to that section.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83178 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30 22:25:37 +00:00
Bob Wilson
812209a58c Add a new virtual EmitStartOfAsmFile method to the AsmPrinter and use this
to emit target-specific things at the beginning of the asm output.  This
fixes a problem for PPC, where the text sections are not being kept together
as expected.  The base class doInitialization code calls DW->BeginModule()
which emits a bunch of DWARF section directives.  The PPC doInitialization
code then emits all the TEXT section directives, with the intention that they
will be kept together. But as I understand it, the Darwin assembler treats
the default TEXT section as a special case and moves it to the beginning of
the file, which means that all those DWARF sections are in the middle of
the text.  With this change, the EmitStartOfAsmFile hook is called before
the DWARF section directives are emitted, so that all the PPC text section
directives come out right at the beginning of the file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83176 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30 22:06:26 +00:00
Bob Wilson
c4c39faa05 Fix a comment typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83174 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30 21:44:42 +00:00
Bob Wilson
b6e4742da7 The AsmPrinter base class contains a DwarfWriter member, so there's no need
for derived AsmPrinters to add another one.  In some cases, fixing this
removes the need to override the doInitialization method.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83170 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30 21:24:45 +00:00
Jim Grosbach
460c482ed3 Clarify comment phrasing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83148 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30 15:23:38 +00:00
Evan Cheng
792e1f6df9 Add a option which would move ld/st multiple pass before post-alloc scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83145 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30 08:53:01 +00:00
Jim Grosbach
d1a5ca6cb1 When checking whether we need to reserve a register for the scavenger,
the size of the saved frame pointer needs to be taken into account.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83136 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30 01:43:29 +00:00
Jim Grosbach
c732adf3a1 Add "isBarrier = 1" to return instructions.
Patch by Sylvere Teissier.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83135 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30 01:35:11 +00:00
Bob Wilson
0fb34683b9 For Darwin, emit all the text section directives together before the dwarf
section directives.  This causes the assembler to put the text sections at
the beginning of the object file, which helps work around a limitation of the
Darwin ARM relocations.  Radar 7255355.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83127 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30 00:23:42 +00:00
David Goodwin
0dad89fa94 Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83122 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30 00:10:16 +00:00
Jim Grosbach
17487ba60d minor cleanup and add clarifying comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83117 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-29 23:17:20 +00:00
Devang Patel
5ccdd10b1a Remove std::string uses from DebugInfo interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83083 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-29 18:40:58 +00:00
Evan Cheng
fa1be5d991 Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83058 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-29 07:07:30 +00:00
Jim Grosbach
ec9eef4a15 Adjust processFunctionBeforeCalleeSavedScan() to correctly reserve a stack
slot for the register scavenger when compiling Thumb1 functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83023 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-28 22:08:06 +00:00
Evan Cheng
fd847118ed Fix Thumb2 IT block pass bug. t2MOVi32imm may not be the start of a IT block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83008 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-28 20:47:15 +00:00
Jakob Stoklund Olesen
26207e5bf1 Introduce the TargetInstrInfo::KILL machine instruction and get rid of the
unused DECLARE instruction.

KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83006 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-28 20:32:26 +00:00
Bob Wilson
522ce97532 Pass the optimization level when constructing the ARM instruction selector.
Otherwise, it is always set to "default", which prevents debug info from
even being generated during isel.  Radar 7250345.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82988 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-28 14:30:20 +00:00
Evan Cheng
5adb66a646 Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
instruction. This makes it re-materializable.

Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82982 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-28 09:14:39 +00:00
Anton Korobeynikov
b0d8d78138 Fix thinko in my recent movt commit: it's not safe to remat movt, since it has input reg argument.
Disable rematting of it for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82975 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-28 07:26:46 +00:00
Anton Korobeynikov
6a2fa325c1 Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.
This should be better than single load from constpool.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82948 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-27 23:52:58 +00:00
Dan Gohman
ae03af2663 LBRX no longer has an explicit SrcValueSDNode operand, so the type
operand is now at index 2, rather than 3. This fixes the
"Invalid child # of SDNode!" failures on PowerPC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82942 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-27 23:17:47 +00:00
Tilmann Scheller
8ff95de83c Use explicit structs instead of std::pair to map callee saved regs to spill slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82909 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-27 17:58:47 +00:00
Evan Cheng
e298ab26b1 Enable pre-regalloc load / store multiple pass for Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82893 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-27 09:46:04 +00:00
Evan Cheng
72c158f908 Really remove this option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82838 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-26 02:49:49 +00:00
Evan Cheng
8981572662 Remove a couple of unused command line options.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82837 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-26 02:45:45 +00:00
Evan Cheng
8f05c1004a Add comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82836 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-26 02:43:36 +00:00
Anton Korobeynikov
d1c37f5b20 Regenerate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82814 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 22:53:17 +00:00
Evan Cheng
eef490f459 Code clean up and prepare for Thumb2 support. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82805 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 21:44:53 +00:00
Dan Gohman
c76909abfe Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
   This eliminates MachineInstr's std::list member and allows the data to be
   created by isel and live for the remainder of codegen, avoiding a lot of
   copying and unnecessary translation. This also shrinks MemSDNode.
 - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
   fields for MachineMemOperands.
 - Change MemSDNode to have a MachineMemOperand member instead of its own
   fields with the same information. This introduces some redundancy, but
   it's more consistent with what MachineInstr will eventually want.
 - Ignore alignment when searching for redundant loads for CSE, but remember
   the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 20:36:54 +00:00
Dan Gohman
602b0c8c17 Rename getTargetNode to getMachineNode, for consistency with the
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82790 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 18:54:59 +00:00
David Goodwin
658ea60997 Finish scheduling itineraries for NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82788 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 18:38:29 +00:00
Bob Wilson
c8ce2d4cb9 Add some comments to clarify things that I discovered this week.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82773 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 16:34:46 +00:00
Bob Wilson
0035f9c3b9 pr4926: ARM requires the stack pointer to be aligned, even for leaf functions.
For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public
interface" it must be 8-byte aligned.  For the older ARM APCS ABI, the stack
alignment is just always 4 bytes.  For X86, we currently align SP at
entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment
is needed at other times, such as for a leaf function.

After discussing this with Dan, I decided to go with the approach of adding
a new "TransientStackAlignment" field to TargetFrameInfo.  This value
specifies the stack alignment that must be maintained even in between calls.
It defaults to 1 except for ARM, where it is 4.  (Some other targets may
also want to set this if they have similar stack requirements. It's not
currently required for PPC because it sets targetHandlesStackFrameRounding
and handles the alignment in target-specific code.) The existing StackAlignment
value specifies the alignment upon entry to a function, which is how we've
been using it anyway.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82767 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 14:41:49 +00:00
Dan Gohman
6acaaa8f32 Don't try to use pre-indexed addressing with sthbrx/stwbrx
instructions. This fixes a PowerPC bug exposed by some unrelated
changes I'm working on.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82743 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 00:57:30 +00:00
Jim Grosbach
3d6cb88a64 Start of revamping the register scavenging in PEI. ARM Thumb1 is the driving
interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.

Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.

For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82734 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24 23:52:18 +00:00
Chris Lattner
fe03dbeaa3 unconditionally request MMI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82716 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24 21:45:57 +00:00
David Goodwin
1f52895692 Make the end-of-itinerary mark explicit. Some cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82709 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24 20:22:50 +00:00
David Goodwin
127221fbdc Checkpoint NEON scheduling itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82657 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-23 21:38:08 +00:00