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6339 Commits

Author SHA1 Message Date
Argyrios Kyrtzidis
8c8b9ee8c8 Revert r111082. No warnings for this common pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111102 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-15 10:27:23 +00:00
Eric Christopher
c0b2a2018a Rework how the non-sse2 memory barrier is lowered so that the 
encoding is correct for the built-in assembler.

Based on a patch from Chris.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111083 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-14 21:51:50 +00:00
Argyrios Kyrtzidis
7268d97ae6 Add ATTRIBUTE_UNUSED to methods that are not supposed to be used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111082 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-14 21:35:10 +00:00
Chris Lattner
132929aa9e improve indentation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111073 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-14 17:26:09 +00:00
Bruno Cardoso Lopes
30baa63474 Add comments to some pattern fragments in x86 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111041 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-13 20:39:01 +00:00
Dale Johannesen
1b4051095d Revert 110491. While not wrong, it was based on a 
misanalysis and is undesirable.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111028 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-13 18:43:45 +00:00
Bruno Cardoso Lopes
bb0a9489e0 Fix comment to reflect code, and remove an unused argument 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111022 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-13 17:50:47 +00:00
Bruno Cardoso Lopes
bbadd39bbb Improve comment to make explicit why not to touch this could before JIT goes MC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111021 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-13 17:44:10 +00:00
Eric Christopher
63f02ac349 Revert last patch and r110954 as I meant to. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111001 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-13 02:37:50 +00:00
Eric Christopher
4404c00db6 Revert r110954 for now, pseudo instructions can't make it through to the JIT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111000 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-13 02:30:00 +00:00
Bruno Cardoso Lopes
64baddc0f2 Some small clean-up: use of pseudo instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110954 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 20:55:18 +00:00
Bruno Cardoso Lopes
642eb02045 - Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary. 
- Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too.
- Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX.
- Add a testcase for a simple 128-bit zero vector creation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110946 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 20:20:53 +00:00
Bruno Cardoso Lopes
6da9cee0f1 Define AVX 128-bit pattern versions of SET0PS/PD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110937 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 18:20:59 +00:00
Bruno Cardoso Lopes
4d04362813 Fix comment order 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110898 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 02:08:52 +00:00
Bruno Cardoso Lopes
8c05a850f4 Begin to support some vector operations for AVX 256-bit intructions. The long 
term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110897 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 02:06:36 +00:00
Daniel Dunbar
09062b1672 MC/X86/AsmParser: Give an explicit error message when we reject an instruction 
because it could have an ambiguous suffix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110890 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 00:55:42 +00:00
Daniel Dunbar
f1e29d4c21 MC/AsmParser: Push the burdon of emitting diagnostics about unmatched 
instructions onto the target specific parser, which can do a better job.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110889 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 00:55:38 +00:00
Daniel Dunbar
4f98f83459 tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl', 
target specific parsers can adapt the TargetAsmParser to this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110888 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 00:55:32 +00:00
Jakob Stoklund Olesen
d29583bd32 Fix <rdar://problem/8282498> even if it doesn't reproduce on trunk. 
When a register is defined by a partial load:

  %reg1234:sub_32 = MOV32mr <fi#-1>; GR64:%reg1234

That load cannot be folded into an instruction using the full 64-bit register.
It would become a 64-bit load.

This is related to the recent change to have isLoadFromStackSlot return false on
a sub-register load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110874 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 23:08:22 +00:00
Dan Gohman
d881627d33 Use ISD::ADD instead of ISD::SUB with a negated constant. This 
avoids trouble if the return type of TD->getPointerSize() is
changed to something which doesn't promote to a signed type,
and is simpler anyway.

Also, use getCopyFromReg instead of getRegister to read a
physical register's value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110835 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 18:14:00 +00:00
Daniel Dunbar
b3cb696794 MCAsmParser: Add dump() hook to MCParsedAsmOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110790 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:37:04 +00:00
Bruno Cardoso Lopes
045573ce21 Add AVX matching patterns to Packed Bit Test intrinsics. 
Apply the same approach of SSE4.1 ptest intrinsics but
create a new x86 node "testp" since AVX introduces
vtest{ps}{pd} instructions which set ZF and CF depending
on sign bit AND and ANDN of packed floating-point sources.

This is slightly different from what the "ptest" does.
Tests comming with the other 256 intrinsics tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110744 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 23:25:42 +00:00
Bruno Cardoso Lopes
9f798e9a9e Add AVX movnt{pd,ps,dq} 256-bit intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110650 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 02:49:24 +00:00
Bruno Cardoso Lopes
fcfcca1d9b Add AVX movmsk 256-bit intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110648 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 02:34:56 +00:00
Bruno Cardoso Lopes
405f11b300 Support AVX 256-bit load and store intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110645 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 01:43:16 +00:00
Bruno Cardoso Lopes
6719784148 Patterns to match AVX cmp instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110633 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 00:13:20 +00:00
Bruno Cardoso Lopes
533a7df02d Add matching patterns for vblend AVX intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110630 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 00:02:05 +00:00
Eric Christopher
5cb33a384f Wording. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110618 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-09 22:52:47 +00:00
Bruno Cardoso Lopes
93f6c1ec6e Add VCVTPD2PS, VCVTPS2DQ, VCVTPS2PDY, VCVTTPD2DQY, VCVTTPS2DQ and VCVTPD2DQ 256-bit conversion intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110608 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-09 21:51:56 +00:00
Bruno Cardoso Lopes
8468157278 Add patterns to AVX conversions instructions. Do that instead of declaring more intructions whenever is possible, more coming 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110605 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-09 21:24:59 +00:00
Oscar Fuentes
4951870e04 CMake: eliminated unnecessary target_link_libraries. 
Next time the build is broken due to wrong library dependencies, just
try building again (if you are on some Unix and are building all LLVM
targets) or ask someone to commit the regenerated LLVMLibDeps.cmake.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110593 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-09 20:33:08 +00:00
Bruno Cardoso Lopes
ad4910429c Memory version of vcvtdq2pd intrinsic 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110582 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-09 18:20:14 +00:00
Bruno Cardoso Lopes
251871ca66 Patterns to match vinsert, vbroadcast, vmovmask and vcvtdq2pd AVX intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110580 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-09 18:03:43 +00:00
Dale Johannesen
7f6eb639bd Use sdmem and sse_load_f64 (etc.) for the vector 
form of CMPSD (etc.)  Matching a 128-bit memory
operand is wrong, the instruction uses only 64 bits
(same as ADDSD etc.)  8193553.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110491 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-07 00:33:42 +00:00
Bruno Cardoso Lopes
4945dd8314 Patterns to match AVX 256-bit vzero intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110480 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-06 22:10:01 +00:00
Bruno Cardoso Lopes
bd2d90f5a5 Patterns to match AVX 256-bit permutation intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110468 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-06 20:03:27 +00:00
Owen Anderson
90c579de5a Reapply r110396, with fixes to appease the Linux buildbot gods. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-06 18:33:48 +00:00
Bruno Cardoso Lopes
9c3806461c Patterns to match AVX 256-bit horizontal arithmetic intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110427 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-06 02:10:30 +00:00
Bruno Cardoso Lopes
9c09f16a53 Patterns to match AVX 256-bit arithmetic intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110425 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-06 01:52:29 +00:00
Owen Anderson
1f74590e9d Revert r110396 to fix buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110410 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-06 00:23:35 +00:00
Eric Christopher
e74a088d92 Add an option to always emit realignment code for a particular module. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110404 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-05 23:57:43 +00:00
Owen Anderson
9ccaf53ada Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static 
ID member as the sole unique type identifier.  Clean up APIs related to this change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110396 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-05 23:42:04 +00:00
Bruno Cardoso Lopes
ac09835a22 Support very basic (doesn't include ABI support in the front-end, varags, ...) 256-bit argument passing and return for AVX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110394 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-05 23:35:51 +00:00
Eric Christopher
505656c6a2 Handle the memory barrier pseudo that goes to nothing for the JIT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110371 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-05 20:04:36 +00:00
Eric Christopher
da93b2cb8f Set hasSideEffects on the 64-bit no-sse memory barrier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110369 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-05 19:54:59 +00:00
Eric Christopher
280f96c508 Be a little bit more specific about target for the memory barrier 
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110360 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-05 18:36:20 +00:00
Eric Christopher
c34ea3770e Handle the pseudo in MCInstLower. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110359 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-05 18:34:30 +00:00
Eric Christopher
b6729dc0ef Make x86-64 membarriers work without sse and clean up some of the 
uses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110274 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-04 23:03:04 +00:00
Eli Friedman
7752442bfa PR7814: Truncates cannot be ignored for signed comparisons. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110268 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-04 22:40:58 +00:00
Devang Patel
5c1d941f00 Add DEBUG message. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110224 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-04 18:06:05 +00:00
Benjamin Kramer
56d23947ca Enable COFF writer on mingw32 and cygwin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110200 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-04 15:32:40 +00:00
Benjamin Kramer
c575283675 Print an error message when someone tries -integrated-as on an unsupported target. 
- The COFF backend doesn't support MingW/Cygwin at the moment, it'll report an
  error, but it's still much better than random assertions from the MachO backend.
- We want to make ELF the default eventually, it's what the majority of targets use.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110197 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-04 13:16:30 +00:00
Chris Lattner
656f6800b2 fix a win64 encoding problem, patch by Cameron Esfahani! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110164 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-03 22:49:22 +00:00
Michael J. Spencer
0cd1ee2308 MC: Remove HasAbsolutizedSet from WindowsX86AsmBackend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109949 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-31 07:21:44 +00:00
Michael J. Spencer
e2195d8b35 Add relax all support to the COFF object streamer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109947 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-31 06:22:29 +00:00
Bruno Cardoso Lopes
98f985607b Support all 128-bit AVX vector intrinsics. Most part of them I already 
declared during the addition of the assembler support, the additional
changes are:
- Add missing intrinsics
- Move all SSE conversion instructions in X86InstInfo64.td to the SSE.td file.
- Duplicate some patterns to AVX mode.
- Step into PCMPEST/PCMPIST custom inserter and add AVX versions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109878 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-30 19:54:33 +00:00
Bruno Cardoso Lopes
5b7dab83e9 Fix typo! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109877 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-30 19:41:24 +00:00
Jakob Stoklund Olesen
b2eeed7464 Revert r109652, and remove the offending assert in loadRegFromStackSlot instead. 
We do sometimes load from a too small stack slot when dealing with x86 arguments
(varargs and smaller-than-32-bit args). It looks like we know what we are doing
in those cases, so I am going to remove the assert instead of artifically
enlarging stack slot sizes.

The assert in storeRegToStackSlot stays in. We don't want to write beyond the
bounds of a stack slot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109764 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-29 17:42:27 +00:00
Jakob Stoklund Olesen
4c010ec851 Create a fixed stack object for varargs that is as large as any register. 
The size of this object isn't used for anything - technically it is of variable
size.

This avoids a false positive from the assert in
X86InstrInfo::loadRegFromStackSlot, and fixes PR7735.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109652 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-28 20:55:38 +00:00
Nate Begeman
51409214d7 Implement a vectorized algorithm for <16 x i8> << <16 x i8> 
This is about 4x faster and smaller than the existing scalarization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109566 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-28 00:21:48 +00:00
Nate Begeman
bdcb5afb77 ~40% faster vector shl <4 x i32> on SSE 4.1 Larger improvements for smaller types coming in future patches. 
For:

define <2 x i64> @shl(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
entry:
  %shl = shl <4 x i32> %r, %a                     ; <<4 x i32>> [#uses=1]
  %tmp2 = bitcast <4 x i32> %shl to <2 x i64>     ; <<2 x i64>> [#uses=1]
  ret <2 x i64> %tmp2
}

We get:

_shl:                                   ## @shl
	pslld	$23, %xmm1
	paddd	LCPI0_0, %xmm1
	cvttps2dq	%xmm1, %xmm1
	pmulld	%xmm1, %xmm0
	ret

Instead of:

_shl:                                   ## @shl
	pshufd	$3, %xmm0, %xmm2
	movd	%xmm2, %eax
	pshufd	$3, %xmm1, %xmm2
	movd	%xmm2, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm2
	pshufd	$1, %xmm0, %xmm3
	movd	%xmm3, %eax
	pshufd	$1, %xmm1, %xmm3
	movd	%xmm3, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm3
	punpckldq	%xmm2, %xmm3
	movd	%xmm0, %eax
	movd	%xmm1, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm2
	movhlps	%xmm0, %xmm0
	movd	%xmm0, %eax
	movhlps	%xmm1, %xmm1
	movd	%xmm1, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm0
	punpckldq	%xmm0, %xmm2
	movdqa	%xmm2, %xmm0
	punpckldq	%xmm3, %xmm0
	ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109549 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-27 22:37:06 +00:00
Michael J. Spencer
dfd30187c6 Make MC use Windows COFF on Windows and add tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109494 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-27 06:46:15 +00:00
Jakob Stoklund Olesen
81c7b19f04 The isLoadFromStackSlot and isStoreToStackSlot have no way of reporting 
subregister operands like this:

%reg1040:sub_32bit<def> = MOV32rm <fi#-2>, 1, %reg0, 0, %reg0, %reg1040<imp-def>; mem:LD4[FixedStack-2](align=8)

Make them return false when subreg operands are present. VirtRegRewriter is
making bad assumptions otherwise.

This fixes PR7713.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109489 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-27 04:17:01 +00:00
Jakob Stoklund Olesen
516cd4575e Add assertions that expose the PR7713 miscompilation: Accessing a stack slot 
with a too-big register class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109488 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-27 04:16:58 +00:00
Evan Cheng
dee81010eb On x86, f32 / f64 nodes share the same registers as 128-bit vector values. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109450 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-26 21:50:05 +00:00
Bruno Cardoso Lopes
3c45734274 Temporary hack to let codegen assert or generate poor code in case 
we are using AVX and no AVX version of the desired intruction is present,
this is better for incremental dev (without fallbacks it's easier to spot
what's missing). Not sure this is the best hack thought (we can also disable
all HasSSE* predicates by dinamically marking them 'false' if AVX is present)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109434 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-26 21:01:18 +00:00
Evan Cheng
70017e44cd Add an ILP scheduler. This is a register pressure aware scheduler that's 
appropriate for targets without detailed instruction iterineries.
The scheduler schedules for increased instruction level parallelism in
low register pressure situation; it schedules to reduce register pressure
when the register pressure becomes high.

On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2
by 16%.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109300 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-24 00:39:05 +00:00
Bruno Cardoso Lopes
3c8e1bee63 Support x86 "eiz" and "riz" pseudo index registers in the assembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109295 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-24 00:06:39 +00:00
Bruno Cardoso Lopes
f64a7d49a0 Remove trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109276 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 22:15:26 +00:00
Bruno Cardoso Lopes
f528d2b438 Add AVX version of CLMUL instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109248 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 18:41:12 +00:00
Bruno Cardoso Lopes
26a9142bd6 Declare CLMUL as a subtarget feature 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109207 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 01:22:45 +00:00
Bruno Cardoso Lopes
cdae7e8244 Add x86 CLMUL (Carry-less multiplication) cpu feature 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109206 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 01:17:51 +00:00
Bruno Cardoso Lopes
6b7e9168a4 Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109204 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 00:54:35 +00:00
Dale Johannesen
c76d23f2e2 The only supported calling convention for X86-64 uses 
SSE, so we can't return floating point values if this
is disabled.  Detect this error for clang.

With SSE1 only, f64 is a problem; it can be done, but
neither llvm-gcc nor clang has ever generated correct
code for it.  Since nobody noticed this I think it's
OK to treat it as an error for now.

This also handles SSE-sized vectors of floating point.
8207686, 8204109.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109201 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 00:30:35 +00:00
Bruno Cardoso Lopes
06e6e101a0 Fix some AVX instructions which didnt had HasAVX prefix. And also a problem with PINSRW, which was totally wrong because of a typo I introduced previously 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109198 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 00:14:54 +00:00
Bruno Cardoso Lopes
fb583a9842 Add remaining AVX instructions (most of them dealing with GR64 destinations. This complete the assembler support for the general AVX ISA. But we still miss instructions from FMA3 and CLMUL specific feature flags, which are now the next step 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109168 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 21:18:49 +00:00
Chris Lattner
134d8eec87 remove the JIT "NeedsExactSize" feature and supporting logic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109167 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 21:17:55 +00:00
Chris Lattner
0123c1da35 X86MCInstLower now depends on AsmPrinter being around. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109154 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 21:10:04 +00:00
Chris Lattner
456fdaf0ce instead of migrating it to the MC instruction encoder, just 
rip out the implementation of X86InstrInfo::GetInstSizeInBytes.
The code being ripped out just implemented a copy and hacked up
version of the (old) instruction encoder, and is buggy and 
terrible in other ways.  Since "GetInstSizeInBytes" is really 
only there to support the JIT's "NeedsExactSize" hook (which
noone is using), just rip out the code.  I will rip out the
NeedsExactSize hook next.

This resolves rdar://7617809 - switch X86InstrInfo::GetInstSizeInBytes to use X86MCCodeEmitter



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109149 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 21:05:13 +00:00
Chandler Carruth
8a89a6ae9c Attempt to fix linking issues with CMake. Please review other CMake users, 
especially on other platforms. Is there a better way to fix this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109084 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 06:27:45 +00:00
Eric Christopher
9a9d275dc7 Custom lower the memory barrier instructions and add support 
for lowering without sse2.  Add a couple of new testcases.

Fixes a few libgomp tests and latent bugs.  Remove a few todos.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109078 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 02:48:34 +00:00
Eric Christopher
90eb4024ba 80-columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109070 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 00:26:08 +00:00
Nate Begeman
0c07b64fec Make fast isel win64-aware w.r.t. call-clobbered regs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109069 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 00:09:39 +00:00
Bruno Cardoso Lopes
2b69143083 Add more 256-bit forms for a bunch of regular AVX instructions 
Add 64-bit (GR64) versions of some instructions (which are not
described in their SSE forms, but are described in AVX)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109063 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 23:53:50 +00:00
Rafael Espindola
fcbd1a749f Fixes win64. It was broken by a previous patch where I missed the !isWin64 
and then forced every register to be a vr128 on win64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109060 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 23:19:57 +00:00
Chris Lattner
908bafe6fa add some rough support for making mcinst lowering work without an 
asmprinter or mangler around.  This is option #B for killing off 
X86InstrInfo::GetInstSizeInBytes.  Option #A (killing 
"needsexactsize") was sent for consideration to llvmdev.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109056 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 23:03:35 +00:00
Bruno Cardoso Lopes
e29f37f6a1 Add missing AVX convert instructions. Those instructions are not described in their SSE forms (although they exist), but add the AVX forms anyway, so the assembler can benefit from it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109039 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 21:37:59 +00:00
Nate Begeman
c8ea673bc0 Fix a couple issues with Win64 ABI 
1) all registers were spilled as xmm, regardless of actual size
2) win64 abi doesn't do the varargs-size-in-%al thing

Still to look into:

xmm6-15 are marked as clobbered by call instructions on win64 even though they aren't.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109035 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 20:49:52 +00:00
Bruno Cardoso Lopes
928fc3b4a0 Avoid AVX instructions to be selected instead of its SSE form 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109032 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 20:38:42 +00:00
Eric Christopher
dab4dac2a0 Pulling out previous patch, must've run the tests in 
the wrong directory.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109005 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 09:23:56 +00:00
Eric Christopher
87f41370a8 Lower MEMBARRIER on x86 and support processors without SSE2. 
Fixes a pile of libgomp failures in the llvm-gcc testsuite due
to the libcall not existing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109004 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 09:05:23 +00:00
Bruno Cardoso Lopes
cf6ca03128 Add AVX only vzeroall and vzeroupper instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109002 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 08:56:24 +00:00
Bruno Cardoso Lopes
7d7d15a159 Add new AVX vpermilps, vpermilpd and vperm2f128 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108984 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 03:07:42 +00:00
Bruno Cardoso Lopes
4b13f3cf3d Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to support it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108983 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 02:46:58 +00:00
Bruno Cardoso Lopes
1154f426d7 Add new AVX vextractf128 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108964 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 23:19:02 +00:00
Chris Lattner
6e8154354f make asmprinter optional, even though passing in null will cause things to explode right now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108955 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 22:45:33 +00:00
Chris Lattner
cb63ecba31 continue pushing dependencies around. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108952 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 22:35:40 +00:00
Chris Lattner
c0115b5ca1 reduce X86MCInstLower dependencies on asmprinter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108950 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 22:30:53 +00:00
Chris Lattner
0c13cf36ad pass around MF, not MMI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108949 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 22:26:07 +00:00
Chris Lattner
7648bd428b cleanups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108947 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 22:23:57 +00:00