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Author SHA1 Message Date
Dale Johannesen
e330ae5b32 Change JIT for different layout of fp80. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67629 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-24 17:35:45 +00:00
Dan Gohman
e1c5267aec Add a testcase for the scheduling heuristic introduced in r67586. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67622 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-24 16:38:27 +00:00
Chris Lattner
e2f7bf8e2d more tidying: name the components of PhysReg in the case when 
the target constraint specifies a specific physreg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67618 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-24 15:27:37 +00:00
Chris Lattner
b3b4484e3d Tidy a bit more. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67617 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-24 15:25:07 +00:00
Chris Lattner
fc9d161f16 simplify this code a bit now that "allocation to a vreg class" can never 
fail.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67616 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-24 15:22:11 +00:00
Dan Gohman
a96dc14968 I was convinced that it's ok to allow a second i8 return value 
to be returned in DL. LLVM's multiple-return-value support is
not ABI-conforming; front-ends that wish to have code emitted
that conforms to an ABI are currently expected to make
arrangements for this on their own rather than assuming that
multiple-return-values will automatically do the right thing.
This commit doesn't fundamentally change this situation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67588 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-24 01:04:34 +00:00
Dan Gohman
8f4aa333d0 Minor compile-time optimization; don't bother checking 
canClobberPhysRegDefs if the successor node doesn't
clobber any physical registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67587 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-24 00:50:07 +00:00
Dan Gohman
002b44f1d7 Add a pre-pass to the burr-list scheduler which makes adjustments to 
help out the register pressure reduction heuristics in the case of
nodes with multiple uses. Currently this uses very conservative
heuristics, so it doesn't have a broad impact, but in cases where it
does help it can make a big difference.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67586 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-24 00:49:12 +00:00
Evan Cheng
f1c0ae9de5 Do not emit comments unless -asm-verbose. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67580 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-24 00:17:40 +00:00
Dale Johannesen
16581bf931 Use a SmallPtrSet instead of std::set. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67578 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 23:39:20 +00:00
Evan Cheng
5d088fee7c Fix a bug in spill weight computation. If the alias is a super-register, and the super-register is in the register class we are trying to allocate. Then add the weight to all sub-registers of the super-register even if they are not aliases. 
e.g. allocating for GR32, bh is not used, updating bl spill weight.                                                                                                        
     bl should get the same spill weight otherwise it will be choosen                                                                                              
     as a spill candidate since spilling bh doesn't make ebx available.
This fix PR2866.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67574 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 22:57:19 +00:00
Ted Kremenek
13b9bf9022 Add sanity check in Clang TableGen backend to check if 'Component' is a string. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67565 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 21:54:33 +00:00
Dale Johannesen
1b25cb2416 Fix internal representation of fp80 to be the 
same as a normal i80 {low64, high16} rather
than its own {high64, low16}.  A depressing number
of places know about this; I think I got them all.
Bitcode readers and writers convert back to the old
form to avoid breaking compatibility.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67562 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 21:16:53 +00:00
John Mosby
ad20778705 README.txt: test commit w/blank line appended 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67560 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 21:00:45 +00:00
Dan Gohman
fa9afef7ea When unfolding a load during scheduling, the new operator node has 
a data dependency on the load node, so it really needs a
data-dependence edge to the load node, even if the load previously
existed.

And add a few comments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67554 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 20:20:43 +00:00
Evan Cheng
3e744c8bc4 Update test for pr3864. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67545 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 18:27:36 +00:00
Evan Cheng
2824a65550 Fix PR3391 and PR3864. Reg allocator infinite looping. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67544 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 18:24:37 +00:00
Dan Gohman
8cccf0ef0c Don't set SUnit::hasPhysRegDefs to true unless the defs are 
actually have uses, which reflects the way it's used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67540 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 17:39:36 +00:00
Dan Gohman
a5c8ae233e Fix canClobberPhysRegDefs to check all SDNodes grouped together 
in an SUnit, instead of just the first one. This fix is needed
by some upcoming scheduler changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67531 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 16:23:01 +00:00
Dan Gohman
3974667c1a Add a new bit to SUnit to record whether a node has implicit physreg 
defs, regardless of whether they are actually used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67528 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 16:10:52 +00:00
Dan Gohman
f871ccb853 Now that errs() is properly non-buffered, there's no need to 
explicitly flush it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67526 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 15:57:19 +00:00
Dan Gohman
f49f0cdb48 Clarify a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67525 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 15:54:02 +00:00
Dan Gohman
2ba682c7e2 LoopVR is not CFGOnly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67524 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 15:50:52 +00:00
Dan Gohman
a9d71e1319 Enhance LiveValues to work on PHI operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67523 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 15:49:37 +00:00
Dan Gohman
b45088cd96 Make getOperandNumForIncomingValue and getOperandNumForIncomingBlock 
static member functions, and add getIncomingValueNumForOperand
and getIncomingBlockNumForOperand, which are the respective
inverses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67522 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 15:48:29 +00:00
Dan Gohman
2004eb6272 Correct some comments. Operand numbers start at 0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67518 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 15:40:10 +00:00
Evan Cheng
fb11288109 Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67512 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 08:01:15 +00:00
Evan Cheng
7d6d4b360f Do not fold away subreg_to_reg if the source register has a sub-register index. That means the source register is taking a sub-register of a larger register. e.g. On x86 
%RAX<def> = ...
%RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3
The first def is defining RAX, not EAX so the top bits were not zero-extended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67511 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 07:19:58 +00:00
Chris Lattner
a8bd27ff66 fix a bug Alexei Svitkine pointed out. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67510 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 06:46:20 +00:00
Chris Lattner
eab5cb3b55 When we restore signal handlers, restore them back to what they 
were when we came around, not to their default handler.  This 
should fix PR3848


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67509 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 05:55:36 +00:00
Chris Lattner
1c4d8a00ab factorize signal registration, part of PR3848. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67508 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 05:42:29 +00:00
Dan Gohman
3aff0a63f9 Fix a grammaro in a comment that Bill noticed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67507 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 05:02:44 +00:00
Chris Lattner
640e7c6d07 tt'ify. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67505 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 04:53:34 +00:00
Chris Lattner
4bd3d7e17c VC++ 6.0 is not future work :) 
Do not recommend llvm::OStream anymore.  Use raw_ostream or MemoryBuffer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67504 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 04:52:53 +00:00
Dan Gohman
82f84159e0 Add comments explaining why there's only one register for 
i8 return values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67502 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 04:28:24 +00:00
Evan Cheng
a38ff646bc Missed this as part of r67451. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67500 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 03:45:56 +00:00
Chris Lattner
dae2206390 Fix PR3860 by correcting a predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67473 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-22 19:22:53 +00:00
Duncan Sands
19527c6ef3 Add some explanations of how apint loads and stores 
work.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67471 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-22 11:33:16 +00:00
Bill Wendling
ad20d3825e Really should pass -dylib to the linker... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67469 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-22 08:56:15 +00:00
Bill Wendling
aca5695223 A dylib should be built as a dylib and not a bundle. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67468 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-22 08:28:45 +00:00
Chris Lattner
4cc2b85861 add method to access a template argument. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67458 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-22 00:18:18 +00:00
Duncan Sands
64da9409cb Factorize out a concept - no functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67454 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-21 21:27:31 +00:00
Evan Cheng
802cd84eb4 Re-commit r67334 and r67349 with fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67451 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-21 18:12:24 +00:00
Chris Lattner
8c7f24a36a add a fastpath to ConstantExpr::getBitCast to handle the case when an obviously 
unneeded bitcast is requested.  This is common for frontends who just unconditionally
cast even if the target is often the right type already.  THis prevents going into
getFoldedCast which switches on the opcode and does a bunch of other stuff before
doing the same opzn.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67435 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-21 06:55:54 +00:00
Chris Lattner
3ee87b6f9d add some inline methods for infix operators on sparse vectors, 
tidy some df iteration stuff, patch by John Mosby!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67428 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-21 05:40:09 +00:00
Bruno Cardoso Lopes
bdfbb74d34 Removed AFGR32 register class 
Handle odd registers allocation in FGR32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67422 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-21 00:05:07 +00:00
Bob Wilson
2a14c521ca Fix a few more indentation problems and an 80-column violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67416 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-20 23:16:43 +00:00
Bob Wilson
2dc4f54324 No functional changes. Fix indentation and whitespace only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67412 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-20 22:42:55 +00:00
Chris Lattner
344c7c5cc4 Fix instcombine to not introduce undefined shifts when merging two 
shifts together.  This fixes PR3851.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67411 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-20 22:41:15 +00:00
Duncan Sands
ab6b226978 Don't load values out of global constants with weak 
linkage: the value may be replaced with something
different at link time.  (Frontends that want to
allow values to be loaded out of weak constants can
give their constants weak_odr linkage).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67407 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-20 21:53:29 +00:00