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882 Commits

Author SHA1 Message Date
Evan Cheng
e3b8a48d32 Fix PR2596: out of bound reference. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54375 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-05 21:51:46 +00:00
Owen Anderson
b6634e9e27 Update the remaining tests not to use -disable-correct-folding, and remove two 
that couldn't be updated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54359 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-05 18:19:14 +00:00
Owen Anderson
551ddf718c One more -disable-correct-folding case removed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54358 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-05 18:08:56 +00:00
Owen Anderson
2a1f07ea6a Remove another -disable-correct-folding use. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54357 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-05 18:05:58 +00:00
Owen Anderson
d6db225800 Eliminate another use of -disable-correct-folding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54356 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-05 18:03:01 +00:00
Evan Cheng
068b4ff553 Fix PR2568: Fix bug that cause redudant kill marker after its live interval has been extended due to coalescing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54346 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-05 07:10:38 +00:00
Owen Anderson
2b85dc3544 Update these tests to work by disabling the new correct CFG generation. This flag should ONLY be used to for tests like these. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54334 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-04 23:55:29 +00:00
Dan Gohman
6f498b0a8e Fix SDISel lowering of PHI nodes to use ComputeValueVTs. 
This allows it to work correctly on aggregate values.
This fixes PR2623.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54331 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-04 23:42:46 +00:00
Dale Johannesen
3b4c45203e Make sse2 explicit, for non-x86 hosts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54251 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-31 20:16:33 +00:00
Dan Gohman
75dcf08243 Improve dagcombining for sext-loads and sext-in-reg nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54239 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-31 00:50:31 +00:00
Dan Gohman
1053502486 I missed this file in r54223. movzbl is now used instead 
of movzbw here.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54224 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-30 18:23:34 +00:00
Dan Gohman
11ba3b1af6 Reapply r54147 with a constraint to only use the 8-bit 
subreg form on x86-64, to avoid the problem with x86-32
having GPRs that don't have 8-bit subregs.

Also, change several 16-bit instructions to use 
equivalent 32-bit instructions. These have a smaller
encoding and avoid partial-register updates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54223 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-30 18:09:17 +00:00
Mon P Wang
e3b3a7241c Added support for overloading intrinsics (atomics) based on pointers 
to different address spaces.  This alters the naming scheme for those
intrinsics, e.g., atomic.load.add.i32 => atomic.load.add.i32.p0i32


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54195 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-30 04:36:53 +00:00
Dan Gohman
7ba145b0b4 Revert 54147. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54148 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-29 01:02:18 +00:00
Dan Gohman
b1e8cad61e Add x86 isel patterns to match what would be a ZERO_EXTEND_INREG operation, 
which is represented in codegen as an 'and' operation. This matches them
with movz instructions, instead of leaving them to be matched by and
instructions with an immediate field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54147 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-28 22:18:25 +00:00
Dan Gohman
6c4942641f Fix embedded CRLF characters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54125 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-27 18:37:58 +00:00
Nate Begeman
907f46a81f Fix test RUN line 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54040 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-25 19:08:59 +00:00
Nate Begeman
fb8ead0c20 Disable mov{L, LP, HP, HLP, *DUP} shuffles for mmx 
mmx needs its own fancy shuffle logic based on unpack; for now we get correct but awful code.

Also commit Mon Ping's VSETCC patch


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54039 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-25 19:05:58 +00:00
Dan Gohman
1f335e3139 This test needs -aggressive-remat enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54015 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-25 15:25:32 +00:00
Dan Gohman
6d69ba8a69 Enable rematerialization of constants using AliasAnalysis::pointsToConstantMemory, 
and knowledge of PseudoSourceValues. This unfortunately isn't sufficient to allow
constants to be rematerialized in PIC mode -- the extra indirection is a
complication.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54000 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-25 00:02:30 +00:00
Dan Gohman
5444c30723 Add target triples so these tests behave as expected on non-darwin hosts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53991 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-24 18:08:01 +00:00
Evan Cheng
2d58bfac59 New test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53971 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-24 00:22:05 +00:00
Evan Cheng
5e6ebaf4d1 Fix PR2485: do all 4-element SSE shuffles in max. of 2 shuffle instructions. 
Based on patch by Nicolas Capens.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53939 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-23 00:22:17 +00:00
Duncan Sands
11e56cb4dc LegalizeTypes support for VSETCC. Fixes PR2575. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53938 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-22 23:54:03 +00:00
Evan Cheng
2925786765 Fix pr2566: incorrect assumption about bit_convert. It doesn't not have to output a vector value. Patch by Nicolas Capens! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53932 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-22 20:42:56 +00:00
Evan Cheng
52672b813e Fix PR2574: implement v2f32 scalar_to_vector. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53927 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-22 18:39:19 +00:00
Bill Wendling
3180e20cda Fix for first part of PR2562. Generate the "pinsrw" instruction for inserts 
into v4i16 vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53807 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-20 02:32:23 +00:00
Anton Korobeynikov
33500e5882 Testcase for PR2549 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53785 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-19 06:31:12 +00:00
Evan Cheng
76a4d58998 Subreg live interval valno may not have a corresponding def machineinstr since it's less precise. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53734 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-17 19:48:53 +00:00
Evan Cheng
d1718252b5 Add nounwind. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53733 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-17 19:48:04 +00:00
Evan Cheng
79a796c2b1 Fix PR2536: a nasty spiller bug. If a two-address instruction uses a register but the use portion of its live range is not part of its liveinterval, it must be defined by an implicit_def. In that case, do not spill the use. e.g. 
8   %reg1024<def> = IMPLICIT_DEF
12  %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2

The live range [12, 14) are not part of the r1024 live interval since it's defined by an implicit def. It will not conflicts with live interval of r1025. Now suppose both registers are spilled, you can easily see a situation where both registers are reloaded before the INSERT_SUBREG and both target registers that would overlap.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53503 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-12 01:56:02 +00:00
Duncan Sands
edfba7e707 Port a shift-by-1 optimization from LegalizeDAG: it 
was presumably added after the rest of the code was
copied to LegalizeTypes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53459 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-11 16:54:57 +00:00
Bill Wendling
71ca353ae6 The frame address on an x86-64 box needs to be offset by -8, not -4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53450 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-11 07:18:52 +00:00
Evan Cheng
331e2bd942 Fix for PR2472. Use movss to set lower 32-bits of a zero XMM vector. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53386 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-10 01:08:23 +00:00
Anton Korobeynikov
091be59220 Testcase for PR2024 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53327 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-09 14:09:41 +00:00
Evan Cheng
1ce75dcbbc Fix two serious LSR bugs. 
1. LSR runOnLoop is always returning false regardless if any transformation is made.
2. AddUsersIfInteresting can create new instructions that are added to DeadInsts. But there is a later early exit which prevents them from being freed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53193 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-07 19:51:32 +00:00
Dale Johannesen
ecdc82a643 Considering predecessors of exit blocks gets 
us a little more tail merging.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52986 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-01 21:50:49 +00:00
Chris Lattner
bd2acd736d test doesn't need eh info 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52811 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-06-27 03:14:20 +00:00
Dale Johannesen
4e97790682 Allow for rounding up of stack frame. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52751 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-06-26 01:55:32 +00:00
Chris Lattner
cda8875433 when we know the signbit of an input to uint_to_fp is zero, 
change it to sint_to_fp on targets where that is cheaper (and
visaversa of course).  This allows us to compile uint_to_fp to:

_test:
	movl	4(%esp), %eax
	shrl	$23, %eax
	cvtsi2ss	%eax, %xmm0
	movl	8(%esp), %eax
	movss	%xmm0, (%eax)
	ret

instead of:

	.align	3
LCPI1_0:					##  double
	.long	0	## double least significant word 4.5036e+15
	.long	1127219200	## double most significant word 4.5036e+15
	.text
	.align	4,0x90
	.globl	_test
_test:
	subl	$12, %esp
	movl	16(%esp), %eax
	shrl	$23, %eax
	movl	%eax, (%esp)
	movl	$1127219200, 4(%esp)
	movsd	(%esp), %xmm0
	subsd	LCPI1_0, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movl	20(%esp), %eax
	movss	%xmm0, (%eax)
	addl	$12, %esp
	ret




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52747 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-06-26 00:16:49 +00:00
Evan Cheng
ab26227c8c - Fix a x86 vector isel bug: illegal transformation of a vector_shuffle into a 
shift.
- Add a readme entry for a missing vector_shuffle optimization that results in
  awful codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52740 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-06-25 20:52:59 +00:00
Mon P Wang
2887310630 Added MemOperands to Atomic operations since Atomics touches memory. 
Added abstract class MemSDNode for any Node that have an associated MemOperand
Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and
atomic.lss => atomic.load.sub


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52706 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-06-25 08:15:39 +00:00
Evan Cheng
601ca4b434 Enable two-address remat by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52701 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-06-25 01:16:38 +00:00
Dale Johannesen
4a103e6d7e v2f32 is now a valid (MMX) type which breaks this 
test (doesn't work for any MMX vector types, it's
not me).  Rewritten to use v2i16 which is generic
and going to stay that way; I think that preserves
the point of the test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52692 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-06-24 22:03:36 +00:00
Evan Cheng
9ef4ca2e81 If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52670 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-06-24 07:10:51 +00:00
Bill Wendling
04eeefb32a Make test work on non-x86 machines (like my G4 PPC). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52619 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-06-23 06:16:31 +00:00
Evan Cheng
c3417609ae Undo spill weight tweak. Need to investigate the performance regressions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52572 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-06-21 06:45:54 +00:00
Eli Friedman
2c8e64d3e4 Fix a bug with <8 x i16> shuffle lowering on X86 where parts of the 
shuffle could be skipped.  The check is invalid because the loop index i 
doesn't correspond to the element actually inserted. The correct check is
already done a few lines earlier, for whether the element is already in 
the right spot, so this shouldn't have any effect on the codegen for 
code that was already correct.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52486 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-06-19 06:09:51 +00:00
Evan Cheng
0d46d753f9 New test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52483 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-06-19 01:50:24 +00:00
Evan Cheng
72d255aff9 This also got better (55 - 51 instructions). But doing one more re-materialization. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52482 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-06-19 01:50:13 +00:00