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1914 Commits

Author SHA1 Message Date
Vladimir Medic
e925f7dbbf This patch implements Mips load/store instructions from/to coprocessor 2. Test cases are added. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190780 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-16 10:29:42 +00:00
Reed Kotler
6febf857f6 Expand the mask capability for deciding which functions are mips16 and mips32 
so it can be better used for general interoperability testing between mips32
and mips16.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190762 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-15 02:09:08 +00:00
Zoran Jovanovic
dcc425c630 Fixed bug when generating Load Upper Immediate microMIPS instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190746 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-14 07:35:41 +00:00
Zoran Jovanovic
ab48d10eff Support for microMIPS DIV instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190745 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-14 07:15:21 +00:00
Zoran Jovanovic
47b33528d1 Support for misc microMIPS instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190744 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-14 06:49:25 +00:00
Zoran Jovanovic
906ae15d5f Test commit to verify that commit access works. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190676 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-13 10:08:05 +00:00
Joey Gouly
715d98d657 Add an instruction deprecation feature to TableGen. 
The 'Deprecated' class allows you to specify a SubtargetFeature that the
instruction is deprecated on.

The 'ComplexDeprecationPredicate' class allows you to define a custom
predicate that is called to check for deprecation.
For example:
  ComplexDeprecationPredicate<"MCR">

would mean you would have to define the following function:
  bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
                             std::string &Info)

Which returns 'false' for not deprecated, and 'true' for deprecated
and store the warning message in 'Info'.

The MCTargetAsmParser constructor was chaned to take an extra argument of
the MCInstrInfo class, so out-of-tree targets will need to be changed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190598 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-12 10:28:05 +00:00
Daniel Sanders
f2eb1e4286 [mips][msa] Added support for matching mulv, nlzc, sll, sra, srl, and subv from normal IR (i.e. not intrinsics) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190518 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-11 11:58:30 +00:00
Daniel Sanders
2ac1282921 [mips][msa] Added support for matching fadd, fdiv, flog2, fmul, frint, fsqrt, and fsub from normal IR (i.e. not intrinsics) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190512 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-11 10:51:30 +00:00
Daniel Sanders
ece929d623 [mips][msa] Added support for matching div_[su] from normal IR (i.e. not intrinsics) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190509 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-11 10:38:58 +00:00
Daniel Sanders
68831cbd41 [mips][msa] Added support for matching addv from normal IR (i.e. not intrinsics) 
The corresponding intrinsic is now lowered into equivalent IR (ISD::ADD) before instruction selection.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190507 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-11 10:28:16 +00:00
Daniel Sanders
ddfbd58054 [mips][msa] Separate the configuration of int/float vector types since they will diverge soon 
No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190506 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-11 10:15:48 +00:00
Daniel Sanders
8857294192 [mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsics 
The elements of the operands should be half the width of the elements of
the result.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190505 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-11 09:59:17 +00:00
Eli Friedman
ae43dac300 Fix unused variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190448 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-10 23:18:14 +00:00
Daniel Sanders
436f64567c [mips][msa] Removed unsupported dot product instructions (dotp_[su].b) 
The dotp_[su].b instructions never existed in any revision of the MSA spec.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190398 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-10 09:51:43 +00:00
Vladimir Medic
b15da6dc09 Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of register when PFU is 32 bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190397 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-10 09:50:01 +00:00
Vladimir Medic
798cdc6af1 Remove obsolete code from MipsAsmParser.cpp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190396 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-10 09:39:55 +00:00
Akira Hatanaka
2dd3afc5e6 [mips] When double precision loads and stores are split into two i32 loads and 
stores, make sure the load or store that accesses the higher half does not have
an alignment that is larger than the offset from the original address.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190318 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-09 17:59:32 +00:00
Bill Wendling
c3cee57f7d Generate compact unwind encoding from CFI directives. 
We used to generate the compact unwind encoding from the machine
instructions. However, this had the problem that if the user used `-save-temps'
or compiled their hand-written `.s' file (with CFI directives), we wouldn't
generate the compact unwind encoding.

Move the algorithm that generates the compact unwind encoding into the
MCAsmBackend. This way we can generate the encoding whether the code is from a
`.ll' or `.s' file.

<rdar://problem/13623355>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190290 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-09 02:37:14 +00:00
Akira Hatanaka
3e6758541b [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double 
precision loads and stores as well as reg+imm double precision loads and stores.

Previously, expansion of loads and stores was done after register allocation,
but now it takes place during legalization. As a result, users will see double
precision stores and loads being emitted to spill and restore 64-bit FP registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190235 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-07 00:52:30 +00:00
Akira Hatanaka
d65d2fde4e [mips] Place parentheses around && to silence warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190234 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-07 00:26:26 +00:00
Akira Hatanaka
1abf0afdd4 [mips] Add definition of instruction "drotr32" (double rotate right plus 32). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190232 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-07 00:18:01 +00:00
Akira Hatanaka
69f8e0935a [mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit 
into a 5-bit or 6-bit field.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190226 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-07 00:02:02 +00:00
Akira Hatanaka
997c5dead8 [mips] Define "trap" as a pseudo instruction that turns into "break 0, 0". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190224 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 23:52:46 +00:00
Akira Hatanaka
cd3c1b9af9 [mips] Delete unused classes and defs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190221 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 23:42:58 +00:00
Akira Hatanaka
1d04ca7987 [mips] Make "b" (unconditional branch) a pseudo. "b" is an assembly idiom, which is 
equivalent to "beq $zero, $zero, offset".




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190220 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 23:40:15 +00:00
Akira Hatanaka
77e1ebd18f [mips] Set instruction itineraries of loads, stores and conditional moves. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190219 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 23:28:24 +00:00
Daniel Sanders
a86062c4b1 [mips][msa] Indentation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190156 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 13:25:06 +00:00
Daniel Sanders
5cb39b22fb [mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance 
Tested with 'llvm-tblgen -print-records' which outputs identical records before
and after this patch.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190155 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 13:15:05 +00:00
Vladimir Medic
638382e6f1 This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190154 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 13:08:00 +00:00
Daniel Sanders
3aaa3e31aa [mips][msa] Made the operand register sets optional for the VEC formats 
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190153 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 13:01:47 +00:00
Vladimir Medic
dadd1fba32 This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190152 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:53:21 +00:00
Daniel Sanders
9e935a77a5 [mips][msa] Made the operand register sets optional for the ELM_INSVE formats 
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190151 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:50:52 +00:00
Daniel Sanders
b9987d1aa1 [mips][msa] Made the operand register sets optional for the 3RF_4RF format 
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190150 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:44:13 +00:00
Vladimir Medic
bf7f7b5e0e This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190148 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:41:17 +00:00
Daniel Sanders
888497d8a2 [mips][msa] Made the operand register sets optional for the 3RF formats 
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190146 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:32:57 +00:00
Daniel Sanders
6976d75415 [mips][msa] Made the operand register sets optional for the 3R_4R format 
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190145 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:30:43 +00:00
Vladimir Medic
a674463aac This patch adds support for microMIPS disassembler and disassembler make check tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190144 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:30:36 +00:00
Daniel Sanders
99d02d1325 [mips][msa] Made the operand register sets optional for the 2RF format 
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190143 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:28:13 +00:00
Daniel Sanders
d31c238372 [mips][msa] Made the operand register sets optional for the I8 format 
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190142 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:25:47 +00:00
Daniel Sanders
7d3da67611 [mips][msa] Made the operand register sets optional for the I5 and SI5 formats 
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190141 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:23:19 +00:00
Daniel Sanders
bfb9bab243 [mips][msa] Made the operand register sets optional for the BIT_[BHWD] formats 
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190140 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:10:24 +00:00
Daniel Sanders
e3273b3275 [mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element size 
No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190134 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 11:01:38 +00:00
Daniel Sanders
cc538affd2 [mips][msa] Made the operand register sets optional for the 3R format 
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190133 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 10:59:24 +00:00
Daniel Sanders
3f1acd55a8 [mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment. 
No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190131 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 10:55:15 +00:00
Reed Kotler
b83c66eb5e Make sure we don't generate stubs for any of these functions because they 
don't exist in libc. This is really not the right way to solve this problem;
but it's not clear to me at this time exactly what is the right way.
If we create stubs here, they will cause link errors because these functions
do not exist in libc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189727 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-01 04:12:59 +00:00
Reed Kotler
c673f9c6fe Fix a problem with dual mips16/mips32 mode. When the underlying processor 
has hard float, when you compile the mips32 code you have to make sure
that it knows to compile any mips32 routines as hard float. I need to clean
up the way mips16 hard float is specified but I need to first think through
all the details. Mips16 always has a form of soft float, the difference being
whether the underlying hardware has floating point. So it's not really
necessary to pass the -soft-float to llvm since soft-float is always true
for mips16 by virtue of the fact that it will not register floating point
registers. By using this fact, I can simplify the way this is all handled.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189690 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-30 19:40:56 +00:00
Daniel Sanders
3c380d5e28 [mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v 
These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes,
are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as
a branch/mov sequence to evaluate to 0 or 1.

Note: The resulting code is sub-optimal since it doesnt seem to be possible
to feed the result of an intrinsic directly into a brcond. At the moment
it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily
evaluates the boolean twice.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189478 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-28 12:14:50 +00:00
Daniel Sanders
2fd3e67dc6 [mips][msa] Added load/store intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189476 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-28 12:04:29 +00:00
Daniel Sanders
abbcf3bd47 [mips][msa] Added move.v 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189471 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-28 10:44:47 +00:00