6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-08 06:32:24 +00:00
Code Issues Projects Releases Wiki Activity
95,971 Commits 39 Branches 0 Tags
Commit Graph

10 Commits

Author SHA1 Message Date
Vincent Lejeune
bb25a01d23 R600: Non vector only instruction can be scheduled on trans unit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189980 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-04 19:53:46 +00:00
Tom Stellard
0991c314d7 R600: Expand vector float operations for both SI and R600 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188596 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-16 23:51:24 +00:00
Tom Stellard
692ee102eb R600: Add 64-bit float load/store support 
* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions

Tom Stellard:
  - Mark vec2 operations as expand.  The addition of a vec2 register
    class made them all legal.

Patch by: Dmitry Cherkassov

Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187582 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-01 15:23:42 +00:00
Tom Stellard
6b3f6a744a Revert "R600: Non vector only instruction can be scheduled on trans unit" 
This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187526 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-31 20:43:27 +00:00
Vincent Lejeune
98ce62780e R600: Non vector only instruction can be scheduled on trans unit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187514 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-31 19:31:56 +00:00
Tom Stellard
a7eea0568c R600: Use KCache for kernel arguments 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186918 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-23 01:48:18 +00:00
Vincent Lejeune
8f9fbd67c3 R600: Support schedule and packetization of trans-only inst 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185268 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-29 19:32:43 +00:00
Vincent Lejeune
76fc2d077f R600: Use bottom up scheduling algorithm 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182129 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-17 16:50:56 +00:00
Vincent Lejeune
92f24d403f R600: Prettier asmPrint of Alu 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180956 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 21:52:30 +00:00
Tom Stellard
3abd23bac5 R600: Reorganize lit tests and document how they should be organized 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179828 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 02:10:53 +00:00