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4092 Commits

Author SHA1 Message Date
Chris Lattner
f74e25f60c Revert r102300/102301, which serious broke objc apps. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102359 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 18:30:45 +00:00
Chris Lattner
044698b39a Fix PR6921: globals were not getting correctly rounded up to their 
preferred alignment unless they were common or some other special
case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102300 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-25 05:30:43 +00:00
Dan Gohman
1d367988e2 Generalize LSR's OptimizeMax to handle the new kinds of max expressions 
that indvars may use, now that indvars is recognizing le and ge loops.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102235 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-24 03:13:44 +00:00
Stuart Hastings
56dda57679 Per Chris, fuse four trivial tests using grep (r102199) into one that uses FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102216 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-23 22:12:57 +00:00
Dan Gohman
6e8fd90602 Change TargetData's algorithm for computing defualt vector type 
alignment to match what's used in clang and GCC for __alignof, rather
than trying to guess what Legalize is going to be doing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102206 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-23 19:41:15 +00:00
Stuart Hastings
e3ff9ba40c Add some missing x86 patterns for movdq2q. Fixes two (LLVM-)GCC DejaGNU testcases. Radar 6881029. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102199 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-23 19:03:32 +00:00
Dan Gohman
fafb890ee2 Fix LSR to tolerate cases where ScalarEvolution initially 
misses an opportunity to fold add operands, but folds them
after LSR has separated them out. This fixes rdar://7886751.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102157 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-23 01:55:05 +00:00
Jim Grosbach
3a1287b470 Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield 
extraction. This fixes PR5998.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102144 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-22 23:24:18 +00:00
Evan Cheng
e3dd8550c6 Do not try to optimize a copy that has already been marked for deletion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102027 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 20:57:54 +00:00
Evan Cheng
e566763b19 Implement -disable-non-leaf-fp-elim which disable frame pointer elimination 
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101984 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 03:18:23 +00:00
Evan Cheng
30fdb5c2ac - Clean up some crappy code which deals with coalescing of copies which look at 
extract_subreg / insert_subreg, etc.
- Add support for more aggressive insert_subreg coalescing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101971 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 00:44:22 +00:00
Dan Gohman
bc7588eb68 Add another variant of this test which found a place where 
CodeGen's ComputeMaskedBits was being over-conservative when computing
bits for an ADD.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101963 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 00:19:28 +00:00
Chris Lattner
d6139425f5 teach the x86 address matching stuff to handle 
(shl (or x,c), 3) the same as (shl (add x, c), 3)
when x doesn't have any bits from c set.

This finishes off PR1135.  Before we compiled the block to:
to:

LBB0_3:                                 ## %bb
	cmpb	$4, %dl
	sete	%dl
	addb	%dl, %cl
	movb	%cl, %dl
	shlb	$2, %dl
	addb	%r8b, %dl
	shlb	$2, %dl
	movzbl	%dl, %edx
	movl	%esi, (%rdi,%rdx,4)
	leaq	2(%rdx), %r9
	movl	%esi, (%rdi,%r9,4)
	leaq	1(%rdx), %r9
	movl	%esi, (%rdi,%r9,4)
	addq	$3, %rdx
	movl	%esi, (%rdi,%rdx,4)
	incb	%r8b
	decb	%al
	movb	%r8b, %dl
	jne	LBB0_1

Now we produce:

LBB0_3:                                 ## %bb
	cmpb	$4, %dl
	sete	%dl
	addb	%dl, %cl
	movb	%cl, %dl
	shlb	$2, %dl
	addb	%r8b, %dl
	shlb	$2, %dl
	movzbl	%dl, %edx
	movl	%esi, (%rdi,%rdx,4)
	movl	%esi, 8(%rdi,%rdx,4)
	movl	%esi, 4(%rdi,%rdx,4)
	movl	%esi, 12(%rdi,%rdx,4)
	incb	%r8b
	decb	%al
	movb	%r8b, %dl
	jne	LBB0_1



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101958 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 23:18:40 +00:00
Bill Wendling
b545cde675 Move CodeGen/X86/2010-04-19-DAGCombineCrash.ll into CodeGen/X86/crash.ll. Also 
reduce.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101925 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 18:14:47 +00:00
Chris Lattner
44e05080f8 Bill's change in r95336 broke empty aggregates embedded 
in other types.  fix this by only bumping zero-byte globals
up to a single byte if the *entire global* is zero size,
fixing PR6340.

This also fixes empty arrays etc to be handled correctly,
and only does this on subsection-via-symbols targets (aka
darwin) which is the only place where this matters.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101879 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 06:20:21 +00:00
Chris Lattner
aa2776e934 teach cellspu how to return i8 and i16 from calls, 
patch by Kalle Raiskila!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101875 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 05:36:09 +00:00
Bill Wendling
86c5abb4c0 The visitXOR method can return the same SDNode. If so, we don't want to delete 
it as it's not dead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101855 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 01:25:01 +00:00
Bob Wilson
02170c0034 Fix tests for Neon load/store intrinsics to match the i8* types expected by 
the intrinsics.  The reason for those i8* types is that the intrinsics are
overloaded on the vector type and we don't have a way to declare an intrinsic
where one argument is an overloaded vector type and another argument is a
pointer to the vector element type.  The bitcasts added here will match what
the frontend will typically generate when these intrinsics are used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101840 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 00:17:16 +00:00
Nick Lewycky
a370a44a76 Fix declarations in a few more tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101676 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 21:29:25 +00:00
Chris Lattner
34e9d17d1b fix PR6332, allowing an index of zero into a zero sized array 
even if the element of the array has no size.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101662 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 19:02:33 +00:00
Dan Gohman
9f23dee08c Start function numbering at 0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101638 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 16:29:15 +00:00
Evan Cheng
8d1092be64 Add nounwind. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101613 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 03:43:36 +00:00
Jakob Stoklund Olesen
4b231c5705 Add test case for machine-sink on critical edges 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101416 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 23:19:16 +00:00
Evan Cheng
3a1588a2e3 Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101410 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 22:20:34 +00:00
Jakob Stoklund Olesen
5ef9d76f6f Fix PR6847. RegScavenger should ignore DebugValues. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101392 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 20:28:39 +00:00
Evan Cheng
0ea7d219ec ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908 
llvm is generating poor code for dynamic alloca, I'll fix that later.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101383 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 18:42:28 +00:00
Chris Lattner
e6987587d6 enhance the load/store narrowing optimization to handle a 
tokenfactor in between the load/store.  This allows us to 
optimize test7 into:

_test7:                                 ## @test7
## BB#0:                                ## %entry
	movl	(%rdx), %eax
                                        ## kill: SIL<def> ESI<kill>
	movb	%sil, 5(%rdi)
	ret

instead of:

_test7:                                 ## @test7
## BB#0:                                ## %entry
	movl	4(%esp), %ecx
	movl	$-65281, %eax           ## imm = 0xFFFFFFFFFFFF00FF
	andl	4(%ecx), %eax
	movzbl	8(%esp), %edx
	shll	$8, %edx
	addl	%eax, %edx
	movl	12(%esp), %eax
	movl	(%eax), %eax
	movl	%edx, 4(%ecx)
	ret



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101355 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 06:10:49 +00:00
Chris Lattner
6dc868581b teach codegen to turn trunc(zextload) into load when possible. 
This doesn't occur much at all, it only seems to formed in the case
when the trunc optimization kicks in due to phase ordering.  In that
case it is saves a few bytes on x86-32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101350 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 05:40:59 +00:00
Chris Lattner
efcddc3325 add a simple dag combine to replace trivial shl+lshr with 
and.  This happens with the store->load narrowing stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 05:28:43 +00:00
Chris Lattner
2392ae7d73 Implement rdar://7860110 (also in target/readme.txt) narrowing 
a load/or/and/store sequence into a narrower store when it is
safe.  Daniel tells me that clang will start producing this sort
of thing with bitfields, and this does  trigger a few dozen times
on 176.gcc produced by llvm-gcc even now.

This compiles code like CodeGen/X86/2009-05-28-DAGCombineCrash.ll 
into:

        movl    %eax, 36(%rdi)

instead of:

        movl    $4294967295, %eax       ## imm = 0xFFFFFFFF
        andq    32(%rdi), %rax
        shlq    $32, %rcx
        addq    %rax, %rcx
        movq    %rcx, 32(%rdi)

and each of the testcases into a single store.  Each of them used
to compile into craziness like this:

_test4:
	movl	$65535, %eax            ## imm = 0xFFFF
	andl	(%rdi), %eax
	shll	$16, %esi
	addl	%eax, %esi
	movl	%esi, (%rdi)
	ret




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101343 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 04:48:01 +00:00
Chris Lattner
dc7d6c9ddc further tweak this to do something useful. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101341 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 04:31:42 +00:00
Chris Lattner
23ab896c13 remove undef control flow. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101340 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 04:30:19 +00:00
Jakob Stoklund Olesen
d394e272d2 Remove unneeded types from test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101286 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-14 20:56:09 +00:00
Bob Wilson
164cd8b8d3 Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand 
does not have a legal type.  The legalizer does not know how to handle those
nodes.  Radar 7854640.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101282 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-14 20:45:23 +00:00
Evan Cheng
370aac4a28 Add test for post-ra machine licm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101182 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-13 22:10:03 +00:00
Bob Wilson
6a234f07fa Handle a v2f64 formal parameter that is split between registers and memory 
such that the entire second half is in memory.  Radar 7855014.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101181 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-13 22:03:22 +00:00
Evan Cheng
005de5ef33 Fix test on non-x86 hosts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101163 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-13 18:54:04 +00:00
Evan Cheng
fc5a03e469 Re-apply 101075 and fix it properly. Just reuse the debug info of the branch instruction being optimized. There is no need to --I which can deref off start of the BB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101162 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-13 18:50:27 +00:00
Eric Christopher
97e6992e3e Temporarily revert r101075, it's causing invalid iterator assertions 
in a nightly tester.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101158 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-13 18:37:58 +00:00
Chris Lattner
43ac721e3b add llvm codegen support for -ffunction-sections and -fdata-sections, 
patch by Sylvere Teissier!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101106 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-13 00:36:43 +00:00
Evan Cheng
82865a10f8 Use .set expression for x86 pic jump table reference to reduce assembly relocation. rdar://7738756 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101085 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-12 23:07:17 +00:00
Bill Wendling
8cc21cac89 Third time's a charm... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101081 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-12 22:43:21 +00:00
Bill Wendling
476e62c459 Genericize the label test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101079 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-12 22:40:37 +00:00
Bill Wendling
35fe23157f Correct test to test what I mean it to test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101077 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-12 22:25:42 +00:00
Bill Wendling
2aae6ae572 Micro-optimization: 
If we have this situation:

    jCC  L1
    jmp  L2
L1:
  ...
L2:
  ...

We can get a small performance boost by emitting this instead:

    jnCC L2
L1:
  ...
L2:
  ...

This testcase shows an example of this:

float func(float x, float y) {
    double product = (double)x * y;
    if (product == 0.0)
        return product;
    return product - 1.0;
}



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101075 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-12 22:19:57 +00:00
Evan Cheng
09010a30fd Enable post regalloc machine licm by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101023 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-12 06:25:28 +00:00
Benjamin Kramer
232c8b4d26 Make sure this test tests something. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100879 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-09 19:03:31 +00:00
Bob Wilson
f5c3f8cda5 Add a testcase for svn r100568. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100876 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-09 18:29:29 +00:00
Chris Lattner
dc8446330f "On SPU, variables in the .bss section that are allocated with the .lcomm directive are not aligned on 16 byte boundaries. This causes misaligned loads, as the generated assembly assumes this "default" alignment. 
this patch disables .lcomm in favour of '.local .comm'

Patch by Kalle Raisklia!




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100875 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-09 18:27:03 +00:00
Dan Gohman
5ce1bf9531 Merge a few fast-isel tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100860 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-09 15:03:55 +00:00