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Author SHA1 Message Date
Justin Holewinski
e953a64cb5 PTX: Start fixing function calls 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140378 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 14:31:12 +00:00
Justin Holewinski
d3dec06447 PTX: Remove PTX calling convention files 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140377 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 14:18:27 +00:00
Justin Holewinski
1cde87d202 [PATCH 2/2] PTXInstrInfo.td PTXIntrinsicInstrInfo.td 80 columns 
From 5936c03172e251f12a0332d1033de5718e6e2091 Mon Sep 17 00:00:00 2001
---
 lib/Target/PTX/PTXInstrInfo.td          |  165 ++++++++++++++++++++----------
 lib/Target/PTX/PTXIntrinsicInstrInfo.td |   88 +++++++++++------
 2 files changed, 167 insertions(+), 86 deletions(-)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140376 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 14:18:24 +00:00
Justin Holewinski
27f08fc619 PTX: Generalize handling of .param types 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140375 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 14:18:22 +00:00
Justin Holewinski
04b5ebc74c PTX: Cleanup unused code in the PTXMFInfoExtract pass 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140374 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 14:18:19 +00:00
Duncan Sands
4c19e12d28 Tweak the handling of MERGE_VALUES nodes: remove the need for 
DecomposeMERGE_VALUES to "know" that results are legalized in
a particular order, by passing it the number of the result
being legalized (the type legalization core provides this, it
just needs to be passed on).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140373 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 13:59:22 +00:00
Nadav Rotem
c56d65f63c Vector-Select: Address one of the problems in pr10902. Add handling for the 
integer-promotion of CONCAT_VECTORS.

Test: test/CodeGen/X86/widen_shuffle-1.ll

This patch fixes the above tests (when running in with -promote-elements).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140372 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 09:33:24 +00:00
Craig Topper
4da632e6e0 Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140370 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 06:57:25 +00:00
Akira Hatanaka
aaa9fc2e37 Add definitions of 64-bit int registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140366 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 02:33:15 +00:00
Akira Hatanaka
373e3a4091 Do not rely on the enum values of argument registers A0-A3 being consecutive. 
Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140363 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 00:58:33 +00:00
Eric Christopher
d8282cd64f We're no longer going to bother supporting platforms that don't 
support C89.

We probably didn't support them anyways.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140361 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 00:53:10 +00:00
Eli Friedman
7666c7e4d2 PR10989: Don't print .hidden on Windows. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140356 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 00:13:02 +00:00
Eli Friedman
a6176adc8a PR10991: make fast-isel correctly check whether accessing a global through an alias involves thread-local storage. (I'm not entirely sure how this is supposed to work, but this patch makes fast-isel consistent with the normal isel path.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140355 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 23:41:28 +00:00
Akira Hatanaka
40eda4626d Make changes in instruction and pattern definitions so that tablegen does not 
complain it cannot infer types in patterns. Fix a mistake in definition of 
SDT_MipsExtractElementF64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140354 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 23:31:54 +00:00
Owen Anderson
db01cdd06b Add new files to CMake. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140352 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 23:20:48 +00:00
Dan Gohman
7b316c9327 Fix SimplifySelectCC to add newly created nodes to the DAGCombiner 
worklist, as it may be possible to perform further optimization on them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140349 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 23:01:29 +00:00
Jakob Stoklund Olesen
4bd89873be Add support for GR32 <-> FR32 cross class copies. 
We already support GR64 <-> VR128 copies.  All of these copies break
partial register dependencies by zeroing the high part of the target
register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140348 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 22:45:24 +00:00
Benjamin Kramer
da7d6ccef5 Update CMake build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140347 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 22:38:34 +00:00
Owen Anderson
124e182103 Start stubbing out MCModule and MCAtom, which provide an API for accessing the rich disassembly of a complete object or executable. 
These are very much a work in progress, and not really useful yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140345 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 22:32:22 +00:00
Jakob Stoklund Olesen
08f5cdf5b3 Constrain register classes instead of emitting copies. 
Sometimes register class constraints are trivial, like GR32->GR32_NOSP,
or GPR->rGPR.  Teach InstrEmitter to simply constrain the virtual
register instead of emitting a copy in these cases.

Normally, these copies are handled by the coalescer.  This saves some
coalescer work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140340 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 21:39:34 +00:00
Jakob Stoklund Olesen
91fb536a34 Add a MinNumRegs argument to MRI::constrainRegClass(). 
The function will refuse to use a register class with fewer registers
than MinNumRegs.  This can be used by clients to avoid accidentally
increase register pressure too much.

The default value of MinNumRegs=0 doesn't affect how constrainRegClass()
works.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140339 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 21:39:31 +00:00
Duncan Sands
17470bee5f Synthesize SSE3/AVX 128 bit horizontal add/sub instructions from 
floating point add/sub of appropriate shuffle vectors.  Does not
synthesize the 256 bit AVX versions because they work differently.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140332 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 20:15:48 +00:00
Eli Friedman
d102a03b36 PR10987: add a missed safety check to isSafePHIToSpeculate in scalarrepl. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140327 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 18:56:30 +00:00
Chris Lattner
5d8f43fdda Resynch intro to section with copyright section. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140326 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 18:54:31 +00:00
Akira Hatanaka
98f49c4413 Print parentheses in next line. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140325 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 18:29:29 +00:00
Akira Hatanaka
ebb90dbb54 Change subreg index of AFPR64 from sub_fpeven to sub_32 per Jakob's comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140324 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 18:24:21 +00:00
Akira Hatanaka
95a091a0b6 Define a new sub-register index sub_32 for accessing the 32-bit sub-register of 
a 64-bit integer register. Move the subreg index definitions to the beginning
of the file.





git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140319 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 17:57:32 +00:00
Bill Wendling
711395527e Use the C personality function instead of the C++ personality function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140318 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 17:56:40 +00:00
Akira Hatanaka
26bcc701a2 Print three closing parentheses when Kind is either VK_Mips_GPOFF_HI or 
VK_Mips_GPOFF_LO.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140316 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 17:44:37 +00:00
Akira Hatanaka
d27fda49c4 Add F31 to the set of callee-saved registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140315 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 17:35:03 +00:00
Galina Kistanova
6bbba3cab4 Fix for warnings: ignoring return value of ‘write’, declared with attribute warn_unused_result. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140314 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 17:33:24 +00:00
Akira Hatanaka
4e41416359 Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140313 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 17:26:58 +00:00
Justin Holewinski
4ddde0cba9 PTX: fixup test cases for register changes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140311 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 16:45:51 +00:00
Justin Holewinski
7c9dd62441 PTX: Remove physical register defs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140310 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 16:45:48 +00:00
Justin Holewinski
5422a0f166 PTX: Use .param space for device function return values on SM 2.0+, and attempt 
to fix up parameter passing on SM < 2.0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140309 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 16:45:46 +00:00
Justin Holewinski
05591be5ed PTX: Fix style issues 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140308 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 16:45:43 +00:00
Justin Holewinski
297984d7c6 PTX: Fixup codegen to handle emission of virtual registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140307 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 16:45:40 +00:00
Justin Holewinski
40466cc758 PTX: Customize codegen passes in backend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140306 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 16:45:37 +00:00
Justin Holewinski
247ee00bce PTX: Add new PTX-specific register allocator that keeps virtual registers 
instead of allocating physical registers.

This is part of a work-in-progress overhaul of the PTX register allocation scheme.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140305 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 16:45:33 +00:00
Garrison Venn
85500714c4 Converted Exception demo over to using new 3.0 landingpad instruction. This 
was compiled and tested on OS X 10.7.1. It was not tested on LINUX. In 
addition the defined OLD_EXC_SYSTEM was not tested with this version.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140303 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 15:45:14 +00:00
Garrison Venn
aae66fad05 This is a hack to get the demo working with the new 3.0 exception 
infrastructure. As this makes the demo no longer a demo, and especially not a 
demo on how to use the llvm exception mechanism, this hack will shortly be 
changed to use the new 3.0 exception infrastructure. However for the time being 
this demo is an example on how to use the AutoUpgrade 
UpgradeExceptionHandling(...) function on < 3.0 exception handling code.                          


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140301 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 14:07:50 +00:00
Craig Topper
adf01b3f18 Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140299 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 07:01:50 +00:00
Akira Hatanaka
bb7d289aeb Add definition of 64-bit floating registers used for Mips64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140297 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 03:48:47 +00:00
Benjamin Kramer
2c2ccbf108 The SSE version differences for fmin/fmax are more involved than I thought. 
- x87: no min or max.
- SSE1: min/max for single precision scalars and vectors.
- SSE2: min/max for single and double precision scalars and vectors.
- AVX: as SSE2, but also supports the wider ymm vectors. (this is covered by the isTypeLegal check)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140296 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 03:27:22 +00:00
Akira Hatanaka
e33ca9ce1f Add enums and functions for symbols Mips64 uses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140295 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 03:09:07 +00:00
Benjamin Kramer
74f3501d15 X86: Don't form min/max nodes if the target is missing SSE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140294 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 03:01:42 +00:00
Akira Hatanaka
459cad2dfd Mips64 aligns stack on 16-byte boundary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140292 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 02:53:37 +00:00
Akira Hatanaka
c56f5ea4c3 Remove unnecessary condition check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140291 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 02:41:29 +00:00
Owen Anderson
6126870193 Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140284 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 23:53:44 +00:00
Owen Anderson
e136872970 Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140283 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 23:44:46 +00:00