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2500 Commits

Author SHA1 Message Date
Evan Cheng
e9e2ba05de Model some vld3 instructions with REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103437 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-10 21:26:24 +00:00
Evan Cheng
603afbfe2a Model vld2 / vst2 with reg_sequence. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103411 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-10 17:34:18 +00:00
Jim Grosbach
4b77f6a85a Clean up the conditional for handling of sign_extend_inreg based on 
whether the extract instructions are available.

rdar://7956878



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103277 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 18:34:55 +00:00
Evan Cheng
435d499177 Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103235 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 02:04:02 +00:00
Evan Cheng
07a6d9391c Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103234 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 01:54:08 +00:00
Evan Cheng
c10b5afbe8 Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103218 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 00:24:52 +00:00
Dan Gohman
34dcc6fadc Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 
doesn't have to guess.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 20:33:48 +00:00
Evan Cheng
746ad69e08 Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 19:06:44 +00:00
Bob Wilson
429009b0f1 Add a missing break statement to fix unintentional fall-through 
(replacing the previous patch for the same issue).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103183 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 16:05:26 +00:00
Jim Grosbach
d31f00b7f7 Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103181 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 15:32:49 +00:00
Shantonu Sen
eae216c6d3 Fix "warning: extra ';' inside a struct or union" when building llvm with clang 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103179 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 14:57:47 +00:00
Evan Cheng
b63387afc6 Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103172 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 06:36:08 +00:00
Dan Gohman
1ef7c82128 Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103163 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 05:08:57 +00:00
Eric Christopher
f865cb5c1f Revert r103156 since it was breaking the build bots. 
Reverse-merging r103156 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMRegisterInfo.h
U    lib/Target/ARM/ARMBaseRegisterInfo.cpp
U    lib/Target/ARM/ARMBaseInstrInfo.cpp
U    lib/Target/ARM/ARMRegisterInfo.td



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103159 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 02:29:06 +00:00
Evan Cheng
9c35ee2099 Fix an obvious bug in isMoveInstr. It needs to return sub-register indices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103157 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 01:54:03 +00:00
Evan Cheng
4ffc22ae00 Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103156 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 01:52:03 +00:00
Evan Cheng
d31c5496d7 Cosmetic changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103155 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 01:34:11 +00:00
Evan Cheng
7f2f436267 storeRegToStackSlot has forgotten about QPR_8 register class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103154 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 01:32:54 +00:00
Jim Grosbach
29402132f3 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack 
instructions to subtarget features and update tests to reflect.
PR5717.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 23:44:43 +00:00
Evan Cheng
676b2dfd27 Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103124 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 22:15:40 +00:00
Jim Grosbach
b1dc393bd5 Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by 
Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103119 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 20:44:35 +00:00
Evan Cheng
de8aa4ed9c Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103104 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 18:28:36 +00:00
Evan Cheng
94cc6d3a2b With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103047 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 20:39:49 +00:00
Evan Cheng
826bdfa603 Do not pre-allocate for registers which form a REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103041 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 20:38:12 +00:00
Jim Grosbach
6e62b4ef14 rdar://7937137 - dbg values not being handled in thumb1 version of 
eliminateFrameIndex(), leading to llvm_unreachable() assertion failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102980 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 00:11:37 +00:00
Dan Gohman
af1d8ca44a Get rid of the EdgeMapping map. Instead, just check for BasicBlock 
changes before doing phi lowering for switches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-01 00:01:06 +00:00
Evan Cheng
8601a3d4de Frame index can be negative. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 01:13:30 +00:00
Jim Grosbach
d100755bab Add sizes non-floating point versions for the eh sjlj intrinsic expansions. 
rdar://7895451



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102526 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 20:33:09 +00:00
Bob Wilson
5dfa87ecc6 Handle register-to-register copies within the tGPR class. 
Radar 7896289


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102396 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 23:20:08 +00:00
Dale Johannesen
3f282aa94b Handle target-specific form of DBG_VALUE in AsmPrinter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102373 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 20:07:31 +00:00
Evan Cheng
62b50656ce Add ARM specific emitFrameIndexDebugValue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102324 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 07:39:25 +00:00
Jim Grosbach
3a1287b470 Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield 
extraction. This fixes PR5998.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102144 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-22 23:24:18 +00:00
Johnny Chen
c048f1d12c Modified some assert() msg strings; no other functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102008 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 18:37:48 +00:00
Evan Cheng
e566763b19 Implement -disable-non-leaf-fp-elim which disable frame pointer elimination 
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101984 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 03:18:23 +00:00
Johnny Chen
52d2b0ed00 Thumb instructions which have reglist operands at the end and predicate operands 
before reglist were not properly handled with respect to IT Block.  Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly.  Add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101974 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 01:01:19 +00:00
Johnny Chen
d6b5d72c0f Better error-handling of getBitFieldInvMask() where msb < lsb (encoding error), 
instead of just asserting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101942 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 21:29:28 +00:00
Johnny Chen
ef37e3abb7 For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111', 
transform the Opcode to the corresponding t2LDR*pci counterpart.

Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101915 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 17:28:50 +00:00
Johnny Chen
3974ade503 Better error-handling for DisassembleThumb2DPModImm() with 2-reg operands where 
d==15 is considered illegal.  Return false instead of assert().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101852 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 01:01:57 +00:00
Johnny Chen
6bcf52f00a More IT instruction error-handling improvements from fuzzing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101839 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 00:15:41 +00:00
Johnny Chen
d0f3c46d16 Better error handling of invalid IT mask '0000', instead of just asserting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101827 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-19 23:02:58 +00:00
Johnny Chen
22e401f5d4 According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1 
Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed.  That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.

Also add a test case for condition field '1111'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101817 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-19 21:19:52 +00:00
Johnny Chen
d6cc53cfe4 Better error-handling for DisassembleThumb2DPSoReg() where the 3-reg operand 
instructions should have Rd (Inst{11-8}) != 0b1111.

Ref: A6.3 32-bit Thumb instruction encoding
     A6.3.11 Data-processing (shifted register)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101788 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-19 17:16:40 +00:00
Johnny Chen
4b7df442a8 ARM disassembler did not react to recent changes to the NEON instruction table. 
VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101784 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-19 16:20:34 +00:00
Anton Korobeynikov
928eb49cae Make processor FUs unique for given itinerary. This extends the limit of 32 
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-18 20:31:01 +00:00
Dan Gohman
3fb150a902 Fix -Wcast-qual warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101655 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 17:42:52 +00:00
Dan Gohman
0d805c33d1 Add const qualifiers to TargetLoweringObjectFile usage. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101640 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 16:44:48 +00:00
Dan Gohman
d858e90f03 Use const qualifiers with TargetLowering. This eliminates several 
const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 15:26:15 +00:00
Dan Gohman
1e93df6f0b Move per-function state out of TargetLowering subclasses and into 
MachineFunctionInfo subclasses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101634 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 14:41:14 +00:00
Bob Wilson
9f3f061d74 Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that this 
may be called when either the source or destination type is i64, and my
change also hadn't fixed the most obvious problem -- assuming that i64 will
only be bitconverted to f64, ignoring the various vector types.
Radar 7873160.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101615 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 05:30:19 +00:00
Johnny Chen
de0ade4939 Cast to (uint64_t) instead of relying on the "ul" suffix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101573 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-16 23:30:28 +00:00