Commit Graph

14693 Commits

Author SHA1 Message Date
Evan Cheng
ea420b20d4 Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104102 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 01:52:25 +00:00
Dan Gohman
7c2e03916c Factor out the code for picking integer arithmetic with immediate
opcodes into a helper function. This fixes a few places in the code
which were not properly selecting the 8-bit-immediate opcodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104091 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 00:53:19 +00:00
Dan Gohman
f8c1ef0510 Teach mode load folding and unfolding code about CMP32ri8 and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104068 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:54:15 +00:00
Bill Wendling
2abc93d0fb Don't eliminate frame pointers from leaf functions if "--disable-fp-elim" is
specified.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:47:08 +00:00
Dan Gohman
e5efbafdac When converting a test to a cmp to fold a load, use the cmp that has an
8-bit immediate field rather than one with a wider immediate field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:42:03 +00:00
Chris Lattner
6db0363bdc make mcinstlower remove all but the first operand to CALL64pcrel32.
The register use operands (e.g. the first argument is passed in a 
register) is currently being modeled as a normal register use,
instead of correctly being an implicit use.  This causes the operand
to get propagated onto the mcinst, which was causing the encoder to
emit a rex prefix byte, which generates an invalid call.

This fixes rdar://7998435


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104062 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:40:18 +00:00
Evan Cheng
28dad2a5ca Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104060 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:31:17 +00:00
Daniel Dunbar
3f40b31256 MC/X86: Implement custom lowering to make sure we match things like
X86::ADC32ri $0, %eax
to
  X86::ADC32i32 $0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104030 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 17:22:24 +00:00
Jakob Stoklund Olesen
535af4a320 ARMBaseRegisterInfo::estimateRSStackSizeLimit() could return prematurely with a
too large limit.

The function would return immediately when finding an addrmode 3/5 instruction.
It needs to keep scanning in case there is an addrmode 6 instruction which drops
the limit to 0.

A test case is very difficult to produce because it will only fail when the
scavenger is used.

rdar://problem/7894847

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103995 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 23:29:23 +00:00
Bill Wendling
53f7602b61 - Set the "HasCalls" flag after instruction selection is finished.
- Change the logic DisableFramePointerElim() to check for the
  -disable-non-leaf-fp-elim before -disable-fp-elim.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103990 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 23:09:50 +00:00
Evan Cheng
47006be498 vmov of immediates are trivially re-materializable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103982 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 21:54:50 +00:00
Daniel Dunbar
9a744e3860 MC: Add dyn_cast support to MCSection.
- Of questionable utility, since in general anything which wants to do this should probably be within a target specific hook, which can rely on the sections being of the appropriate type. However, it can be useful for short term hacks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 21:54:26 +00:00
Eric Christopher
423c9e3e58 Add some section and constant support for darwin TLS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103974 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 21:02:07 +00:00
Bob Wilson
7f43fd84db Fix a regression in 464.h264 for thumb1 and thumb2 nightly tests.
Obvious in retrospect but not fun to debug.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103969 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 20:31:13 +00:00
Evan Cheng
6206124250 Turn on -neon-reg-sequence by default.
Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103960 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 19:51:20 +00:00
Evan Cheng
9c207ac0dc No reason not to run the NEON domain croassing fix up pass in thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103917 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 01:11:46 +00:00
Dale Johannesen
f7f5a2760a Revert 103911; it broke a test that expects bitconvert
<1xi64> -> i64 to work in MMX registers on hosts where -no-sse
is the default (not mine).  The right thing is
to accept this and make i64->f64 conversions go through memory,
but I don't have time right now.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103914 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-16 20:19:04 +00:00
Dale Johannesen
f9b2242927 Make x86-64 64-bit bitconvert work when SSE is not available.
(This worked as of about 6 months ago and I didn't track down
exactly what broke it; I think this fix is appropriate.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103911 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-16 18:22:38 +00:00
Anton Korobeynikov
bd91ea53f8 Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-16 09:15:36 +00:00
Anton Korobeynikov
ded05e34b6 Add support for thiscall calling convention.
Patch by Charles Davis and Steven Watanabe!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103902 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-16 09:08:45 +00:00
Anton Korobeynikov
4878b8415f Generalize the ARM DAG combiner of mul with constants to all power-of-two cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-16 08:54:20 +00:00
Evan Cheng
8f6de385d6 Model vst lane instructions with REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103898 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-16 03:27:48 +00:00
Dale Johannesen
8d908ebd19 Fix uint64->{float, double} conversion to do rounding correctly in 32-bit.
The implementation in LegalizeIntegerTypes to handle this as 
sint64->float + appropriate power of 2 is subject to double rounding,
considered incorrect by numerics people.  Use this implementation only
when it is safe.  This leads to using library calls in some cases
that produced inline code before, but it's correct now.
(EVTToAPFloatSemantics belongs somewhere else, any suggestions?)

Add a correctly rounding (though not particularly fast) conversion
that uses X87 80-bit computations for x86-32.

7885399, 5901940.  This shows up in gcc.c-torture/execute/ieee/rbug.c
in the gcc testsuite on some platforms.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103883 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 18:51:12 +00:00
Anton Korobeynikov
a9790d739a Some cheap DAG combine goodness for multiplication with a particular constant.
This can be extended later on to handle more "complex" constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103881 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 18:16:59 +00:00
Anton Korobeynikov
418d1d954d "trap" pseudo-op turned out to be apple-local.
Temporary emit it as raw bytes until it will be added to binutils as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 17:19:20 +00:00
Evan Cheng
7189fd03fa Model 128-bit vld lane with REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103868 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 07:53:37 +00:00
Evan Cheng
4782b1e2ca v4i64 and v8i64 are only synthesizable when NEON is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103855 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 02:20:21 +00:00
Evan Cheng
06b666c705 Allow TargetLowering::getRegClassFor() to be called on illegal types. Also
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 02:18:07 +00:00
Evan Cheng
7092c2bfcb Model 64-bit lane vld with REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103851 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 01:36:29 +00:00
Evan Cheng
b990a2f249 Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE
instructions.

e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12

After REG_SEQUENCE is eliminated, we are left with:

%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5

The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible, 
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103835 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 23:21:14 +00:00
Evan Cheng
12c24690c7 Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103833 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 22:54:52 +00:00
Bill Wendling
23ead99283 SystemZ really does mean "has calls" and not just "adjusts stack." Go ahead and
replace the check with the appropriate predicate. Modify the testcase to reflect
the correct code. (It should be saving callee-saved registers on the stack
allocated by the calling fuction.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103829 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 22:17:42 +00:00
Dan Gohman
4ee637c730 BR is a barrier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103826 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 22:00:27 +00:00
Bill Wendling
f84d60b649 Several tail call tests apparently rely upon this being "adjusts stack" instead
of "has calls". That's probably wrong, but it needs further
investigation. Revert to the original behavior until this is settled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103824 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 21:58:35 +00:00
Bill Wendling
55ed945bfd This should happen if there are no calls, not if it just doesn't adjust the
stack.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103813 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 21:38:44 +00:00
Bill Wendling
0fc546b053 Revert r103804. The comment is correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103808 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 21:28:24 +00:00
Bill Wendling
d33fa0f9e0 Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103804 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 21:17:29 +00:00
Bill Wendling
b92187a410 Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what
the variable actually tracks.

N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103802 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 21:14:32 +00:00
Dan Gohman
71ea4e5b05 Lowering of atomic instructions can result in operands being
used more than once. If ISel had put a kill flag on one of them,
it's not valid to transfer the kill flag to each new instance.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103799 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 21:01:44 +00:00
Kevin Enderby
c3ce05c594 Fix so "int3" is correctly accepted, added "into" and fixed "int" with an
argument, like "int $4", to not get an Assertion error.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103791 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 19:16:02 +00:00
Evan Cheng
5c6aba2e3a Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103790 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 18:54:59 +00:00
Dan Gohman
effc8c5269 Set isTerminator on TRAP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103778 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 16:46:02 +00:00
Dan Gohman
c0c32ae5c2 Don't use isBarrier for the PowerPC sync instruction. isBarrier is for
control barriers, not memory ordering barriers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103777 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 16:42:16 +00:00
Dan Gohman
7f357ec6d2 Add mayLoad and mayStore flags to instructions which missed them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103776 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 16:34:55 +00:00
Evan Cheng
22c687b642 Added a QQQQ register file to model 4-consecutive Q registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 02:13:41 +00:00
Evan Cheng
7f68719517 Fix comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103749 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 00:21:45 +00:00
Evan Cheng
c4ca40eb5e Add comment about the pseudo registers QQ, each of which is a pair of Q registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103731 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 20:02:08 +00:00
Bob Wilson
1190c14b54 Fix pr7110: For non-Darwin targets UnspilledCS1GPRs may include high registers.
Do not use those for Thumb1 functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103730 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 19:58:24 +00:00
Oscar Fuentes
ed36aac081 CMake: fixes 64 bit Visual Studio IDE build. Fixes bug 4936.
Patch by Dimitry Andric!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103727 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 19:34:06 +00:00
Anton Korobeynikov
61aeed11cd Properly set thread-local flag on globals during cpp emission
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103702 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 07:41:57 +00:00