Commit Graph

102561 Commits

Author SHA1 Message Date
Duncan P. N. Exon Smith
ebb5d29473 Revert "blockfreq: Rewrite BlockFrequencyInfoImpl" (#2)
This reverts commit r206622 and the MSVC fixup in r206626.

Apparently the remotely failing tests are still failing, despite my
attempt to fix the nondeterminism in r206621.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206628 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 17:56:08 +00:00
Greg Fitzgerald
cfb2d0ea10 Fixed llvm-build when no targets are enabled
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206627 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 17:39:50 +00:00
Duncan P. N. Exon Smith
3a9522f7a1 Fixing MSVC after r206622?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206626 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 17:38:01 +00:00
Andrew Trick
939bc92c04 Better comments to explain buffered/unbuffered processor resources.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206625 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 17:35:08 +00:00
Alexey Samsonov
fe030f3dcd [DWARF parser] Refactor fetching DIE address ranges.
Add a helper method to get address ranges specified in a DIE
(either by DW_AT_low_pc/DW_AT_high_pc, or by DW_AT_ranges). Use it
to untangle and simplify the code.

No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206624 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 17:25:46 +00:00
Duncan P. N. Exon Smith
54850bedf2 Reapply "blockfreq: Rewrite BlockFrequencyInfoImpl"
This reverts commit r206556, effectively reapplying commit r206548 and
its fixups in r206549 and r206550.

In an intervening commit I've added target triples to the tests that
were failing remotely [1] (but passing locally).  I'm hoping the mystery
is solved?  I'll revert this again if the tests are still failing
remotely.

[1]: http://bb.pgr.jp/builders/ninja-x64-msvc-RA-centos6/builds/1816

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206622 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 17:22:25 +00:00
Duncan P. N. Exon Smith
1e1954f749 Add some target triples for better determinism
These tests were failing on some buildbots after r206548 (reverted in
r206556), but passing locally.

They were missing target triples, so maybe that's the problem?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206621 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 17:22:19 +00:00
Benjamin Kramer
5dd15cdb83 LineIterator: Add DataTypes.h for int64_t on MSVC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206617 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 16:57:01 +00:00
Benjamin Kramer
f2896111b5 Add some missing includes for various standard library implementations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206616 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 16:46:29 +00:00
Benjamin Kramer
98b539ae65 Make the copy member of StringRef/ArrayRef generic wrt allocators.
Doesn't make sense to restrict this to BumpPtrAllocator. While there
replace an explicit loop with std::equal. Some standard libraries know
how to compile this down to a ::memcmp call if possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206615 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 16:36:15 +00:00
Tim Northover
7b4b261611 AArch64/ARM64: add more NEON tests.
Mostly no testing this time, since they were just wrangling
target-specific intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206613 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 14:54:53 +00:00
Benjamin Kramer
d781e40b6a Allocator: Remove ReferenceAdder hack.
This was a workaround for compilers that had issues with reference
collapsing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206612 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 14:54:51 +00:00
Tim Northover
f34a512a68 ARM64: disable generation of .loh directives outside MachO.
Part of PR19455.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206611 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 14:54:46 +00:00
Tim Northover
9cfd368302 ARM64: don't emit .subsections_via_symbols on ELF.
Part of PR19455.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206610 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 14:54:41 +00:00
Tim Northover
1d5a2ad8a6 ARM64: add extra NEG pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206609 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 14:54:35 +00:00
Tim Northover
936285440b AArch64/ARM64: port more AArch64 tests to ARM64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206592 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 13:16:55 +00:00
Tim Northover
753cfe6172 AArch64/ARM64: add non-scalar lowering for more FCVT operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206591 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 13:16:42 +00:00
Tim Northover
7b4b522ec8 AArch64/ARM64: improve spotting of EXT instructions from VECTOR_SHUFFLE.
We couldn't cope if the first mask element was UNDEF before, which
isn't ideal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206588 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 12:50:58 +00:00
Evgeniy Stepanov
f19e327319 [msan] Add -msan-instrumentation-with-call-threshold.
This flag replaces inline instrumentation for checks and origin stores with
calls into MSan runtime library. This is a workaround for PR17409.

Disabled by default.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206585 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 12:17:20 +00:00
Chandler Carruth
14def55736 [LCG] Remove all of the complexity stemming from supporting copying.
Reality is that we're never going to copy one of these. Supporting this
was becoming a nightmare because nothing even causes it to compile most
of the time. Lots of subtle errors built up that wouldn't have been
caught by any "normal" testing.

Also, make the move assignment actually work rather than the bogus swap
implementation that would just infloop if used. As part of that, factor
out the graph pointer updates into a helper to share between move
construction and move assignment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206583 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 11:02:33 +00:00
Chandler Carruth
d61b3c303c [Allocator] Fix an obvious think-o with the move assignment
implementation of the SpecificBumpPtrAllocator -- we have to actually
move the subobject. =] Noticed when using this code more directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206582 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 11:02:29 +00:00
Chandler Carruth
4c7edb1240 [LCG] Add support for building persistent and connected SCCs to the
LazyCallGraph. This is the start of the whole point of this different
abstraction, but it is just the initial bits. Here is a run-down of
what's going on here. I'm planning to incorporate some (or all) of this
into comments going forward, hopefully with better editing and wording.
=]

The crux of the problem with the traditional way of building SCCs is
that they are ephemeral. The new pass manager however really needs the
ability to associate analysis passes and results of analysis passes with
SCCs in order to expose these analysis passes to the SCC passes. Making
this work is kind-of the whole point of the new pass manager. =]

So, when we're building SCCs for the call graph, we actually want to
build persistent nodes that stick around and can be reasoned about
later. We'd also like the ability to walk the SCC graph in more complex
ways than just the traditional postorder traversal of the current CGSCC
walk. That means that in addition to being persistent, the SCCs need to
be connected into a useful graph structure.

However, we still want the SCCs to be formed lazily where possible.

These constraints are quite hard to satisfy with the SCC iterator. Also,
using that would bypass our ability to actually add data to the nodes of
the call graph to facilite implementing the Tarjan walk. So I've
re-implemented things in a more direct and embedded way. This
immediately makes it easy to get the persistence and connectivity
correct, and it also allows leveraging the existing nodes to simplify
the algorithm. I've worked somewhat to make this implementation more
closely follow the traditional paper's nomenclature and strategy,
although it is still a bit obtuse because it isn't recursive, using
an explicit stack and a tail call instead, and it is interruptable,
resuming each time we need another SCC.

The other tricky bit here, and what actually took almost all the time
and trials and errors I spent building this, is exactly *what* graph
structure to build for the SCCs. The naive thing to build is the call
graph in its newly acyclic form. I wrote about 4 versions of this which
did precisely this. Inevitably, when I experimented with them across
various use cases, they became incredibly awkward. It was all
implementable, but it felt like a complete wrong fit. Square peg, round
hole. There were two overriding aspects that pushed me in a different
direction:

1) We want to discover the SCC graph in a postorder fashion. That means
   the root node will be the *last* node we find. Using the call-SCC DAG
   as the graph structure of the SCCs results in an orphaned graph until
   we discover a root.

2) We will eventually want to walk the SCC graph in parallel, exploring
   distinct sub-graphs independently, and synchronizing at merge points.
   This again is not helped by the call-SCC DAG structure.

The structure which, quite surprisingly, ended up being completely
natural to use is the *inverse* of the call-SCC DAG. We add the leaf
SCCs to the graph as "roots", and have edges to the caller SCCs. Once
I switched to building this structure, everything just fell into place
elegantly.

Aside from general cleanups (there are FIXMEs and too few comments
overall) that are still needed, the other missing piece of this is
support for iterating across levels of the SCC graph. These will become
useful for implementing #2, but they aren't an immediate priority.

Once SCCs are in good shape, I'll be working on adding mutation support
for incremental updates and adding the pass manager that this analysis
enables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206581 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 10:50:32 +00:00
Benjamin Kramer
c32e261a1a X86: Pattern match scalar loads + vcvtph2ps into just vcvtph2ps.
vcvtph2ps only reads the lower 64 bits of the address passed to the
intrinsic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206579 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 10:45:33 +00:00
Chandler Carruth
64eed05a3a Revert r206565 (and r206566 which updated tests).
This commit was attributed to a different person from the person who
posted the patch to the list, and the person who posted it the list
claimed when they did that they were not the author, but that the author
was yet a third person. I don't know what is going on here, but
reverting until the attribution is clear and the author has explicitly
contributed the patch.

Also, the review hasn't really involved any of the MC maintainers and
that seems questionable too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206576 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 09:35:51 +00:00
Tim Northover
fb96efa7dd AArch64/ARM64: port atomics test to ARM64.
Covers quite a few extra instructions (like any of the max/min ones
which were broken until recently on ARM64).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206575 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 09:31:31 +00:00
Tim Northover
0d6995985a AArch64/ARM64: spot a greater variety of concat_vector operations.
Code mostly copied from AArch64, just tidied up a trifle and plumbed
into the ARM64 way of doing things.

This also enables the AArch64 tests which inspired the previous
untested commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206574 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 09:31:27 +00:00
Tim Northover
70b63374f2 ARM64: implement cunning optimisation from AArch64
A vector extract followed by a dup can become a single instruction even if the
types don't match. AArch64 handled this in ISelLowering, but a few reasonably
simple patterns can take care of it in TableGen, so that's where I've put it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206573 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 09:31:20 +00:00
Tim Northover
e7ec66e56b ARM64: spot a vector_shuffle that maps to INS and expand.
Tests will be coming very shortly when all the optimisations needed to
support AArch64's neon-copy.ll file are committed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206572 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 09:31:15 +00:00
Tim Northover
8405c940d3 ARM64: nick some AArch64 patterns for extract/insert -> INS.
Tests will be committed shortly when all optimisations needed to
support AArch64's neon-copy.ll file are supported.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206571 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 09:31:11 +00:00
Tim Northover
66643da8fc AArch64/ARM64: emit all vector FP comparisons as such.
ARM64 was scalarizing some vector comparisons which don't quite map to
AArch64's compare and mask instructions. AArch64's approach of sacrificing a
little efficiency to emulate them with the limited set available was better, so
I ported it across.

More "inspired by" than copy/paste since the backend's internal expectations
were a bit different, but the tests were invaluable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206570 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 09:31:07 +00:00
Tim Northover
937290d7ed AArch64/ARM64: port BSL logic from AArch64 & enable test.
I enhanced it a little in the process. The decision shouldn't really be beased
on whether a BUILD_VECTOR is a splat: any set of constants will do the job
provided they're related in the correct way.

Also, the BUILD_VECTOR could be any operand of the incoming AND nodes, so it's
best to check for all 4 possibilities rather than assuming it'll be the RHS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206569 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 09:31:01 +00:00
Tim Northover
2f5d14af9d AArch64/ARM64: copy byval implementation from AArch64.
It's not actually used to handle C or C++ ABI rules on ARM64, but could well be
emitted by other language front-ends, so it's as well to have a sensible
implementation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206568 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 09:30:52 +00:00
Jiangning Liu
eea662fead Add missing config file for newly added test case introduced by r206563.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206567 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 09:05:50 +00:00
Yaron Keren
188195c3f9 Updated test with register names following r206565.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206566 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 08:50:09 +00:00
Yaron Keren
becde896f5 Patch by Ray Donnelly.
Emit WIN64 SEH registers by name instead of just number.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206565 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 08:03:38 +00:00
Kostya Serebryany
40a9c0f58b [asan] one more workaround for PR17409: don't do BB-level coverage instrumentation if there are more than N (=1500) basic blocks. This makes ASanCoverage work on libjpeg_turbo/jchuff.c used by Chrome, which has 1824 BBs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206564 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 08:02:42 +00:00
Jiangning Liu
a1da819896 This commit allows vectorized loops to be unrolled by a factor of 2 for AArch64.
A new test case is also added for ARM64.

Patched by Z.Zheng



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206563 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 07:57:54 +00:00
Matt Arsenault
1b16515971 R600: Minor cleanups.
Fix indentation, better line wrapping, unused includes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206562 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 07:40:20 +00:00
Lang Hames
c3097bfd9b [ExecutionEngine] Allow JIT clients to enable/disable module verification.
Previously module verification was always enabled, with no way to turn it off.
As of this commit, module verification is on by default in Debug builds, and off
by default in release builds. The default behaviour can be overridden by calling
setVerifyModules(bool) on the JIT instance (this works for both the old JIT, and
MCJIT).

<rdar://problem/16150008>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206561 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 06:48:23 +00:00
Jiangning Liu
bc3655f9c8 This is one of the optimizations ported from ARM64 to AArch64 to address the performance gap between these two back ends. The test case newly added for AArch64 already exists in ARM64.
Patched by Z.Zheng



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206559 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 05:58:09 +00:00
Matt Arsenault
746734df1a R600/SI: Try to use scalar BFE.
Use scalar BFE with constant shift and offset when possible.
This is complicated by the fact that the scalar version packs
the two operands of the vector version into one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206558 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 05:19:26 +00:00
Jiangning Liu
532a5ffe4c This commit enables unaligned memory accesses of vector types on AArch64 back end. This should boost vectorized code performance.
Patched by Z. Zheng



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206557 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 03:58:38 +00:00
Duncan P. N. Exon Smith
c7a3b95c0f Revert "blockfreq: Rewrite BlockFrequencyInfoImpl"
This reverts commits r206548, r206549 and r206549.

There are some unit tests failing that aren't failing locally [1], so
reverting until I have time to investigate.

[1]: http://bb.pgr.jp/builders/ninja-x64-msvc-RA-centos6/builds/1816

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206556 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 02:17:43 +00:00
Justin Bogner
2359d30af6 OnDiskHashTable: Provide iterator_range for keys and data
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206555 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 02:10:26 +00:00
Duncan P. N. Exon Smith
a9da909e57 blockfreq: Really fix r206548 (and r206549)
Turns out this code is dead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206554 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 02:10:09 +00:00
Jim Grosbach
b08b9d7c09 c++11: Tidy up tblgen w/ range loops.
IntrInfoEmitter cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206553 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 02:09:07 +00:00
Jim Grosbach
bfe74b9bfb iterator access to scheduling classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206552 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 02:09:04 +00:00
Jim Grosbach
7b771af259 iterator_range accessor for CodeGenTarget instruction list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206551 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 02:09:02 +00:00
Jim Grosbach
3db76ccd4e iterator based accessors for CodeGenInstruction operand list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206550 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 02:08:58 +00:00
Duncan P. N. Exon Smith
a3610962a9 blockfreq: Fixing MSVC after r206548?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206549 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 02:06:24 +00:00