Commit Graph

64 Commits

Author SHA1 Message Date
Evan Cheng
9fe2009956 Sorry, several patches in one.
TargetInstrInfo:
Change produceSameValue() to take MachineRegisterInfo as an optional argument.
When in SSA form, targets can use it to make more aggressive equality analysis.

Machine LICM:
1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead.
2. Fix a bug which prevent CSE of instructions which are not re-materializable.
3. Use improved form of produceSameValue.

ARM:
1. Teach ARM produceSameValue to look pass some PIC labels.
2. Look for operands from different loads of different constant pool entries
   which have same values.
3. Re-implement PIC GA materialization using movw + movt. Combine the pair with
   a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible
   to re-materialize the instruction, allow machine LICM to hoist the set of
   instructions out of the loop and make it possible to CSE them. It's a bit
   hacky, but it significantly improve code quality.
4. Some minor bug fixes as well.

With the fixes, using movw + movt to materialize GAs significantly outperform the
load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap
and 176.gcc ~10%.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20 08:34:58 +00:00
Evan Cheng
df55fea807 Spill R4 if it's going to be used to restore SP from FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123567 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-16 05:14:33 +00:00
Jim Grosbach
3e333637f1 Thumb1 had two patterns for the same load-from-constant-pool instruction.
Canonicalize on tLDRpci and remove tLDRcp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121920 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 23:52:36 +00:00
Devang Patel
afeaae7a94 If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121059 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06 22:39:26 +00:00
Evan Cheng
ab5c703fdb Fix epilogue codegen to avoid leaving the stack pointer in an invalid
state. Previously Thumb2 would restore sp from fp like this:
mov sp, r7
sub, sp, #4
If an interrupt is taken after the 'mov' but before the 'sub', callee-saved
registers might be clobbered by the interrupt handler. Instead, try
restoring directly from sp:
add sp, #4
Or, if necessary (with VLA, etc.) use a scratch register to compute sp and
then restore it:
sub.w r4, r7, #8
mov sp, r7
rdar://8465407


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119977 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-22 18:12:04 +00:00
Dale Johannesen
8abe08d7f9 These tests are looking for library function names that
appear to differ on Linux.  Try to make them pass on Linux.
Would be good for a Linux person to review this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119572 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17 21:57:32 +00:00
Bob Wilson
54f9256380 Do not use MEMBARRIER_MCR for any Thumb code.
It is only supported for ARM code.  Normally Thumb2 code would use DMB instead,
but depending on how the compiler is invoked (e.g., -mattr=-db) that might be
disabled.  This prevents a "cannot select MEMBARRIER_MCR" error in that
situation.  Radar 8644195

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09 22:50:44 +00:00
Bob Wilson
f74a429816 Overhaul memory barriers in the ARM backend. Radar 8601999.
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain.  It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions.  Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions.  Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 00:54:37 +00:00
Jakob Stoklund Olesen
7eb589d3f9 Try again to disable critical edge splitting in CodeGenPrepare.
The bug that broke i386 linux has been fixed in r115191.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 20:51:52 +00:00
Jakob Stoklund Olesen
08342f2d11 Revert "Disable codegen prepare critical edge splitting. Machine instruction passes now"
This reverts revision 114633. It was breaking llvm-gcc-i386-linux-selfhost.

It seems there is a downstream bug that is exposed by
-cgp-critical-edge-splitting=0. When that bug is fixed, this patch can go back
in.

Note that the changes to tailcallfp2.ll are not reverted. They were good are
required.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 18:43:48 +00:00
Evan Cheng
dd3a41a6b3 Disable codegen prepare critical edge splitting. Machine instruction passes now
break critical edges on demand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114633 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 06:55:34 +00:00
Jim Grosbach
d0bd76b0fb Re-enable usage of the ARM base pointer. r113394 fixed the known failures.
Re-running some nightly testers w/ it enabled to verify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113399 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 20:12:02 +00:00
Jim Grosbach
e1e6d18786 disable for the moment while tracking down a few Thumb2-O0 failure that look
related. (attempt deux, complete w/ test update this time)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113333 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 02:00:34 +00:00
Jim Grosbach
65482b1bb8 Re-apply r112883:
"For ARM stack frames that utilize variable sized objects and have either
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs."

r112986 fixed a latent bug exposed by the above.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112989 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 18:37:12 +00:00
Daniel Dunbar
6a8700301c Revert "For ARM stack frames that utilize variable sized objects and have either", it is breaking oggenc with Clang for ARMv6.
This reverts commit 8d6e29cfda270be483abf638850311670829ee65.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112962 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 15:26:42 +00:00
Jim Grosbach
1755b3964f For ARM stack frames that utilize variable sized objects and have either
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs.

rdar://7352504
rdar://8374540
rdar://8355680



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112883 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02 22:29:01 +00:00
Jim Grosbach
85e75afc8e Update test for 112609
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112610 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 17:58:47 +00:00
Duncan Sands
cdd4f8c7cb Correct bogus module triple specifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112469 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30 10:48:29 +00:00
Jim Grosbach
ae47c6d69e Enable pre-RA virtual frame base register allocation. rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112127 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 00:58:06 +00:00
Evan Cheng
e1f0859789 Fix test and re-enable it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110829 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 17:25:51 +00:00
Dan Gohman
f63fed141e Temporarily disable some failing tests, until they can be
properly investigated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110808 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 15:09:00 +00:00
Evan Cheng
d6b4632256 Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110795 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:51:54 +00:00
Evan Cheng
c7569ed4e4 Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit
instructions: dmb, dsb, isb, msr, and mrs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110786 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:30:38 +00:00
Evan Cheng
11db068721 - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
  instructions).
- Added tests for memory barrier codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:22:01 +00:00
Evan Cheng
ac096808a3 Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function stack frame has a var-sized object.
Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110707 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 19:30:19 +00:00
Daniel Dunbar
4bd828f781 Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FP
register is", it breaks a couple test-suite tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110701 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 18:32:02 +00:00
Evan Cheng
c9aed19747 Fix ARM hasFP() semantics. It should return true whenever FP register is
reserved, not available for general allocation. This eliminates all the
extra checks for Darwin.

This change also fixes the use of FP to access frame indices in leaf
functions and cleaned up some confusing code in epilogue emission.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110655 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 06:26:49 +00:00
Benjamin Kramer
3df1d5c408 Feed the right output into FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108523 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 10:58:02 +00:00
Dale Johannesen
bdc09d9b09 The SelectionDAGBuilder's handling of debug info, on rare
occasions, caused code to be generated in a different order.
All cases I've seen involved float softening in the type
legalizer, and this could be perhaps be fixed there, but
it's better not to generate things differently in the first
place.  7797940 (6/29/2010..7/15/2010).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108484 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 00:02:08 +00:00
Dale Johannesen
f1e309eb48 Propagate the AlignStack bit in InlineAsm's to the
PrologEpilog code, and use it to determine whether
the asm forces stack alignment or not.  gcc consistently
does not do this for GCC-style asms; Apple gcc inconsistently
sometimes does it for asm blocks.  There is no
convenient place to put a bit in either the SDNode or
the MachineInstr form, so I've added an extra operand
to each; unlovely, but it does allow for expansion for
more bits, should we need it.  PR 5125.  Some
existing testcases are affected.
The operand lists of the SDNode and MachineInstr forms
are indexed with awesome mnemonics, like "2"; I may
fix this someday, but not now.  I'm not making it any
worse.  If anyone is inspired I think you can find all
the right places from this patch.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107506 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02 20:16:09 +00:00
Bob Wilson
b5b5057a70 ARM function alignments were off by a power of two. svn 83242 changed
getFunctionAlignment and the corresponding use of that value in the ARM
asm printer, but now we're using the standard asm printer.  The result of
this was that function alignments were dropped completely for Thumb functions.
Radar 8143571.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 22:26:26 +00:00
Benjamin Kramer
a2938e7e5f Fix some tests that didn't test anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106954 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26 20:05:06 +00:00
Evan Cheng
0110ac66eb Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106368 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 01:01:32 +00:00
Rafael Espindola
1e81966626 Remove arm_apcscc from the test files. It is the default and doing this
matches what llvm-gcc and clang now produce.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106221 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 15:18:27 +00:00
Jakob Stoklund Olesen
8a3eab9b20 Remove the local register allocator.
Please use the fast allocator instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106051 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 21:58:33 +00:00
Jakob Stoklund Olesen
85f4fdaed4 Enable a bunch more -regalloc=fast tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 00:11:24 +00:00
Evan Cheng
fb3611daad Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103459 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 07:26:32 +00:00
Dan Gohman
9f23dee08c Start function numbering at 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101638 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 16:29:15 +00:00
Dale Johannesen
b39b7e5ebf Split big test into multiple directories to cater to
those who don't build all targets.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 20:43:35 +00:00
Evan Cheng
fac4f1f181 Enable machine cse pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98132 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10 03:07:41 +00:00
Bob Wilson
516ab96de3 Run the pre-register allocation tail duplication pass by default. Remove
the -pre-regalloc-taildup command-line option, and add a new
-disable-early-taildup option.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93597 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-16 00:29:50 +00:00
Jim Grosbach
2be065a0e8 add testcase for r93564
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93567 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-15 22:27:37 +00:00
Jakob Stoklund Olesen
f8ad5bcdb5 Add test case for the phi reuse patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91642 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:11:44 +00:00
Evan Cheng
2ef9c8a43d More consistent thumb1 asm printing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89328 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-19 06:57:41 +00:00
Evan Cheng
d457e6e9a5 Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86330 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 04:04:34 +00:00
Jim Grosbach
6009751244 Enable allocation of R3 in Thumb1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84563 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 22:57:03 +00:00
Evan Cheng
892597943a Forgot about ARM::tPUSH. It also has a new writeback operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83237 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-02 05:03:07 +00:00
Evan Cheng
10469f8e48 ARM::tPOP and tPOP_RET each has an extra writeback operand now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83214 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 20:54:53 +00:00
Dan Gohman
fce288fc91 Eliminate more uses of llvm-as and llvm-dis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-09 00:09:15 +00:00
Evan Cheng
0e87e23f6e v4, v5 does not support sxtb / sxth.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80322 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-28 00:31:43 +00:00