Eric Christopher
e24d66f525
Rework braindead conditionals I put in yesterday.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111974 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 22:07:27 +00:00
Eric Christopher
9f782d4dcf
Fix thumb2 mode loads to have the correct operand ordering. Add a todo
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to fix this in the port.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111973 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 22:03:02 +00:00
Eric Christopher
882d62e2db
Update comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111887 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 01:10:52 +00:00
Eric Christopher
2012c7bb7b
Fix the opcode and the operands for the load instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111885 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 01:10:04 +00:00
Eric Christopher
f06f309002
Add register class hack that needs to go away, but makes it more obvious
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that it needs to go away. Use loadRegFromStackSlot where possible.
Also, remember to update the value map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111883 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 00:50:47 +00:00
Eric Christopher
cb0b04ba6f
Add some more debugging code, make it more obvious that RegOffset is
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getting an address for an object and select some default values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111871 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 00:07:24 +00:00
Eric Christopher
1dfb4d31e0
Don't need the extra register here.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111864 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23 23:28:04 +00:00
Eric Christopher
8654c71e56
Add some more "get address into register" code and a more TODOs/FIXMEs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23 23:14:31 +00:00
Eric Christopher
7fe55b739c
Add an ARMFunctionInfo member and use it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23 22:32:45 +00:00
Eric Christopher
8300712c1e
Start getting ARM loads/address computation going.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111850 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23 21:44:12 +00:00
Eric Christopher
f762fbe4fa
Fix loop conditionals (MO.isDef() asserts that it's a reg) and
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move some constraints around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111594 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-20 00:36:24 +00:00
Eric Christopher
cb59229a4a
Add a couple of random comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111592 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-20 00:20:31 +00:00
Eric Christopher
979e0a1414
Silence warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111518 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-19 15:35:27 +00:00
Eric Christopher
456144eb14
Add an AddOptionalDefs method and use it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111489 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-19 00:37:05 +00:00
Eric Christopher
0fe7d54732
Copy over some overridden MI wrappers for ARM fast-isel. This is where
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we're adding predicates and optional defs to the MachineInstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111222 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 01:25:29 +00:00
Eric Christopher
038fea5e30
Make arm fast-isel possible to enable via command line.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111219 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 00:46:57 +00:00
Evan Cheng
0944795b8c
ARM fastisel isn't ready.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-26 18:32:55 +00:00
Eric Christopher
ab695889c6
Baby steps towards ARM fast-isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 22:26:11 +00:00
