Commit Graph

111621 Commits

Author SHA1 Message Date
Chandler Carruth
2bbc5ab5eb [PM] Move the analysis registry into the Passes.cpp file and provide
a normal interface for it in Passes.h.

This gives us essentially a single interface for running pass managers
which are provided from the bottom of the LLVM stack through interfaces
at the top of the LLVM stack that populate them with all of the
different analyses available throughout. It also means there is a single
blob of code that needs to include all of the pass headers and needs to
deal with the registry of passes and parsing names.

No functionality changed intended, should just be cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225237 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-06 02:21:37 +00:00
Chandler Carruth
a3376d2d36 [PM] Add a utility to the new pass manager for generating a pass which
is a no-op other than requiring some analysis results be available.

This can be used in real pass pipelines to force the usually lazy
analysis running to eagerly compute something at a specific point, and
it can be used to test the pass manager infrastructure (my primary use
at the moment).

I've also added bit of pipeline parsing magic to support generating
these directly from the opt command so that you can directly use these
when debugging your analysis. The syntax is:

  require<analysis-name>

This can be used at any level of the pass manager. For example:

  cgscc(function(require<my-analysis>,no-op-function))

This would produce a no-op function pass requiring my-analysis, followed
by a fully no-op function pass, both of these in a function pass manager
which is nested inside of a bottom-up CGSCC pass manager which is in the
top-level (implicit) module pass manager.

I have zero attachment to the particular syntax I'm using here. Consider
it a straw man for use while I'm testing and fleshing things out.
Suggestions for better syntax welcome, and I'll update everything based
on any consensus that develops.

I've used this new functionality to more directly test the analysis
printing rather than relying on the cgscc pass manager running an
analysis for me. This is still minimally tested because I need to have
analyses to run first! ;] That patch is next, but wanted to keep this
one separate for easier review and discussion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225236 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-06 02:10:51 +00:00
Rafael Espindola
5165dfdf9a Add a testcase that would have found the problem in r225048.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225235 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-06 01:41:24 +00:00
Eric Christopher
248063bb27 Remove dead variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225233 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-06 01:12:42 +00:00
Eric Christopher
943a34f68b Use the same call off of the TargetMachine rather than the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225232 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-06 01:12:40 +00:00
Eric Christopher
1abeb77588 Rewrite the Mips16HardFloat pass to avoid using the Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225231 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-06 01:12:30 +00:00
Lang Hames
bce877c84c Revert r225048: It broke ObjC on AArch64.
I've filed http://llvm.org/PR22100 to track this issue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225228 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-06 00:54:32 +00:00
Brad Smith
0d3cd751c4 Remove X86 .quad workaround for buggy GNU assembler on OpenBSD / Bitrig.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225227 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-06 00:53:52 +00:00
Duncan P. N. Exon Smith
97d1c07c15 IR: Don't drop MDNode uniquing on null operands
Now that `LLVMContextImpl` can call `MDNode::dropAllReferences()` to
prevent teardown madness, stop dropping uniquing just because an operand
drops to null.

Part of PR21532.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225223 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 23:31:54 +00:00
Duncan P. N. Exon Smith
2f7982026d Revert "Use the integrated assembler by default on 32-bit PowerPC and SPARC"
This reverts commit r225213.  It's failing on multiple buildbots [1][2].

[1]: http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/22032
[2]: http://lab.llvm.org:8080/green/view/Clang/job/clang-stage1-cmake-RA-incremental_check/2357/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225222 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 23:31:51 +00:00
Hal Finkel
38c3e2f5c5 [PowerPC] Fix test to pass on Darwin hosts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225220 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 23:17:43 +00:00
Hal Finkel
a767eed6f1 [PowerPC] Remove old README.txt entry
We no longer generate horrible code for the stated function:

void f(signed char *a, _Bool b, _Bool c) {
  signed char t = 0;
  if (b)  t = *a;
  if (c)  *a = t;
}

for which we now generate:

.L.f:
        andi. 5, 5, 1
        cmpldi 1, 4, 0
        li 5, 0
        beq 1, .LBB0_2
        lbz 5, 0(3)
.LBB0_2:                                # %if.end
        bclr 4, 1, 0
        stb 5, 0(3)
        blr

so we don't need the README.txt entry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225217 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 22:20:22 +00:00
Simon Pilgrim
a5b2142af1 [X86][SSE] lowerVectorShuffleAsByteShift tidyup
Removed local isSequential predicate and use standard helper isSequentialOrUndefInRange instead.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225216 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 22:08:48 +00:00
Hal Finkel
fcfee17911 [PowerPC] Convert a README.txt entry into a better test
We now produce the desired code as noted in the README.txt file (no spurious
or). Remove the README entry and improve the regression test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225214 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 21:53:52 +00:00
Brad Smith
a45b58174f Use the integrated assembler by default on 32-bit PowerPC and SPARC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225213 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 21:48:16 +00:00
Hal Finkel
92a87c67ee [PowerPC] Remove README.txt entry
This entry has been rendered irrelevant now that we have proper CR bit
tracking.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225211 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 21:41:26 +00:00
Colin LeMahieu
e4f1dcdb83 [Hexagon] Adding add/sub with carry, logical shift left by immediate and memop instructions. Removing old defs without bits and updating references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225210 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 21:36:38 +00:00
Hal Finkel
1b84bf2554 [PowerPC] Add a test for truncating a shifted load
We now produce the desired code as noted in the README.txt file. Remove the
README entry and add a regression test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225209 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 21:33:14 +00:00
Frederic Riss
0c36e97b78 Make DIE.h a public CodeGen header.
dsymutil would like to use all the AsmPrinter/MCStreamer infrastructure
to stream out the DWARF. In order to do so, it will reuse the DIE object
and so this header needs to be public.

The interface exposed here has some corners that cannot be used without a
DwarfDebug object, but clients that want to stream Dwarf can just avoid
these.

Differential Revision: http://reviews.llvm.org/D6695

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225208 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 21:29:41 +00:00
Frederic Riss
5a0743e1e8 [dsymutil] Implement the BinaryHolder object and gain archive support.
This object is meant to own the ObjectFiles and their underlying
MemoryBuffer. It is basically the equivalent of an OwningBinary
except that it efficiently handles Archives. It is optimized for
efficiently providing mappings of members of the same archive when
they are opened successively (which is standard in Darwin debug
maps, objects from the same archive will be contiguous).

Of course, the BinaryHolder will also be used by the DWARF linker
once it is commited, but for now only the debug map parser uses it.

With this change, you can run llvm-dsymutil on your Darwin debug build
of clang and get a complete debug map for it.

Differential Revision: http://reviews.llvm.org/D6690

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225207 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 21:29:28 +00:00
NAKAMURA Takumi
27c27a0b61 [autoconf] llvm/cmake/modules/Makefile: Make sure to regenerate LLVMConfig.cmake whenever Makefile is updated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225206 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 21:24:36 +00:00
Hal Finkel
e7d845b709 [PowerPC] Add another test for load/store with update
We now produce the desired code as noted in the README.txt file. Remove the
README entry and add a regression test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225205 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 21:22:42 +00:00
NAKAMURA Takumi
75beb04d36 [autoconf] Export LLVM_LIBDIR_SUFFIX with empty string in LLVMConfig.cmake. tools/llvm-config is also doing so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225204 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 21:14:14 +00:00
Hal Finkel
ccc83e4a08 [PowerPC] Fold i1 extensions with other ops
Consider this function from our README.txt file:

  int foo(int a, int b) { return (a < b) << 4; }

We now explicitly track CR bits by default, so the comment in the README.txt
about not really having a SETCC is no longer accurate, but we did generate this
somewhat silly code:

        cmpw 0, 3, 4
        li 3, 0
        li 12, 1
        isel 3, 12, 3, 0
        sldi 3, 3, 4
        blr

which generates the zext as a select between 0 and 1, and then shifts the
result by a constant amount. Here we preprocess the DAG in order to fold the
results of operations on an extension of an i1 value into the SELECT_I[48]
pseudo instruction when the resulting constant can be materialized using one
instruction (just like the 0 and 1). This was not implemented as a DAGCombine
because the resulting code would have been anti-canonical and depends on
replacing chained user nodes, which does not fit well into the lowering
paradigm. Now we generate:

        cmpw 0, 3, 4
        li 3, 0
        li 12, 16
        isel 3, 12, 3, 0
        blr

which is less silly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225203 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 21:10:24 +00:00
Simon Pilgrim
dd0552884b [X86][SSE] Fixed description for isSequentialOrUndefInRange. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225202 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 21:09:48 +00:00
Colin LeMahieu
ca96263b05 [Hexagon] Adding rounding reg/reg variants, accumulating multiplies, and accumulating shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225201 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 20:56:41 +00:00
Duncan P. N. Exon Smith
d43539c123 IR: Prune arguments to ValueAsMetadata::ValueAsMetadata()
`LLVMContext` isn't actually used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225200 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 20:41:25 +00:00
Colin LeMahieu
27494b0633 [Hexagon] Adding V4 bit manipulating instructions, removing ALU defs without encoding bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225199 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 20:35:54 +00:00
Colin LeMahieu
c8e734a561 [Hexagon] Adding V4 logic-logic instructions and tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225198 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 20:14:58 +00:00
Colin LeMahieu
e48ec2a918 [Hexagon] Adding orand, bitsplit reg/reg, and modwrap instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225197 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 20:04:40 +00:00
Hal Finkel
3ab10c1918 [PowerPC] Remove zexts after i32 ctlz
The 64-bit semantics of cntlzw are not special, the 32-bit population count is
stored as a 64-bit value in the range [0,32]. As a result, it is always zero
extended, and it can be added to the PPCISelDAGToDAG peephole optimization as a
frontier instruction for the removal of unnecessary zero extensions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225192 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 18:52:29 +00:00
Hal Finkel
0ef99720c5 [PowerPC] Remove zexts after byte-swapping loads
lhbrx and lwbrx not only load their data with byte swapping, but also clear the
upper 32 bits (at least). As a result, they can be added to the PPCISelDAGToDAG
peephole optimization as frontier instructions for the removal of unnecessary
zero extensions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225189 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 18:09:06 +00:00
Colin LeMahieu
9e989cf190 [Hexagon] Adding round reg/imm and bitsplit instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225188 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 18:08:21 +00:00
Saleem Abdulrasool
e5f07551f0 SymbolRewriter: use iplist::splice
The swap implementation for iplist is currently unsupported.  Simply splice the
old list into place, which achieves the same purpose.  This is needed in order
to thread the -frewrite-map-file frontend option correctly.  NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225186 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 17:56:32 +00:00
Saleem Abdulrasool
02d601d342 SymbolRewriter: 80-column
Wrap a couple of lines.  NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225185 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 17:56:29 +00:00
Ahmed Bougacha
3c9fb6e1ad [AArch64] Improve codegen of store lane instructions by avoiding GPR usage.
We used to generate code similar to:

  umov.b        w8, v0[2]
  strb  w8, [x0, x1]

because the STR*ro* patterns were preferred to ST1*.
Instead, we can avoid going through GPRs, and generate:

  add   x8, x0, x1
  st1.b { v0 }[2], [x8]

This patch increases the ST1* AddedComplexity to achieve that.

rdar://16372710
Differential Revision: http://reviews.llvm.org/D6202


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225183 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 17:10:26 +00:00
Ahmed Bougacha
c52cd839b9 [AArch64] Improve codegen of store lane 0 instructions by directly storing the subregister.
For 0-lane stores, we used to generate code similar to:

  fmov w8, s0
  str w8, [x0, x1, lsl #2]

instead of:

  str s0, [x0, x1, lsl #2]

To correct that: for store lane 0 patterns, directly match to STR <subreg>0.

Byte-sized instructions don't have the special case for a 0 index,
because FPR8s are defined to have untyped content.

rdar://16372710
Differential Revision: http://reviews.llvm.org/D6772


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225181 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 17:02:28 +00:00
NAKAMURA Takumi
19d9f342ed llvm/test/lit.cfg: have_ld_plugin_support(): Use decode() for stdout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225171 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 14:18:04 +00:00
Karthik Bhat
050064d32c Select lower fsub,fabs pattern to fabd on AArch64
This patch lowers patterns such as-
  fsub   v0.4s, v0.4s, v1.4s
  fabs   v0.4s, v0.4s
to
  fabd  v0.4s, v0.4s, v1.4s
on AArch64.

Review: http://reviews.llvm.org/D6791



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225169 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 13:57:59 +00:00
Charlie Turner
6abfc44aab Parse Tag_compatibility correctly.
Tag_compatibility takes two arguments, but before this patch it would
erroneously accept just one, it now produces an error in that case.

Change-Id: I530f918587620d0d5dfebf639944d6083871ef7d

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225167 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 13:26:37 +00:00
Charlie Turner
b99b8ffb7f Emit the build attribute Tag_conformance.
Claim conformance to version 2.09 of the ARM ABI.

This build attribute must be emitted first amongst the build attributes when
written to an object file. This is to simplify conformance detection by
consumers.

Change-Id: If9eddcfc416bc9ad6e5cc8cdcb05d0031af7657e

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225166 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 13:12:17 +00:00
Karthik Bhat
e239724d12 Select lower sub,abs pattern to sabd on AArch64
This patch lowers patterns such as-
  sub	v0.4s, v0.4s, v1.4s
  abs	v0.4s, v0.4s
to
  sabd	v0.4s, v0.4s, v1.4s
on AArch64.

Review: http://reviews.llvm.org/D6781



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225165 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 13:11:07 +00:00
Michael Kuperstein
25903ef9bc Fix broken test from r225159.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225164 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 12:34:01 +00:00
Chandler Carruth
1ab487fdc7 [PM] Don't run the machinery of invalidating all the analysis passes
when all are being preserved.

We want to short-circuit this for a couple of reasons. One, I don't
really want passes to grow a dependency on actually receiving their
invalidate call when they've been preserved. I'm thinking about removing
this entirely. But more importantly, preserving everything is likely to
be the common case in a lot of scenarios, and it would be really good to
bypass all of the invalidation and preservation machinery there.
Avoiding calling N opaque functions to try to invalidate things that are
by definition still valid seems important. =]

This wasn't really inpsired by much other than seeing the spam in the
logging for analyses, but it seems better ot get it checked in rather
than forgetting about it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225163 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 12:32:11 +00:00
Chandler Carruth
040ca449b2 [PM] Add names and debug logging for analysis passes to the new pass
manager.

This starts to allow us to test analyses more easily, but it's really
only the beginning. Some of the code here is still untestable without
manual changes to create analysis passes, but I wanted to factor it into
a small of chunks as possible.

Next up in order to be able to test things are, in no particular order:
- No-op analyses passes so we don't have to use real ones to exercise
  the pass maneger itself.
- Automatic way of generating dummy passes that require an analysis be
  run, including a variant that calls a 'print' method on a pass to make
  it even easier to print out the results of an analysis.
- Dummy passes that invalidate all analyses for their IR unit so we can
  test invalidation and re-runs.
- Automatic way to print each analysis pass as it is re-run.
- Automatic but optional verification of analysis passes everywhere
  possible.

I'm not claiming I'll get to all of these immediately, but that's what
is in the pipeline at some stage. I'm fleshing out exactly what I need
and what to prioritize by working on converting analyses and then trying
to test the conversion. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225162 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 12:21:44 +00:00
Craig Topper
9bf73516cb Replace several 'assert(false' with 'llvm_unreachable' or fold a condition into the assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225160 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 10:15:49 +00:00
Jiangning Liu
614fe873ce Fixed a bug in memory dependence checking module of loop vectorization. The following loop should not be vectorized with current algorithm.
{code}
// loop body
   ... = a[i]          (1)
    ... = a[i+1]       (2)
 .......
a[i+1] = ....          (3)
   a[i] = ...          (4)
{code}

The algorithm tries to collect memory access candidates from AliasSetTracker, and then check memory dependences one another. The memory accesses are unique in AliasSetTracker, and a single memory access in AliasSetTracker may map to multiple entries in AccessAnalysis, which could cover both 'read' and 'write'. Originally the algorithm only checked 'write' entry in Accesses if only 'write' exists. This is incorrect and the consequence is it ignored all read access, and finally some RAW and WAR dependence are missed.

For the case given above, if we ignore two reads, the dependence between (1) and (3) would not be able to be captured, and finally this loop will be incorrectly vectorized.

The fix simply inserts a new loop to find all entries in Accesses. Since it will skip most of all other memory accesses by checking the Value pointer at the very beginning of the loop, it should not increase compile-time visibly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225159 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 10:08:58 +00:00
Michael Gottesman
16c2e77337 Convert SmallMapVector from a class to a struct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225158 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 08:55:19 +00:00
Craig Topper
a5ba79effa [X86] Remove the predicates from the register forms of the 2-byte inc and dec instructions. Remove the 32-bit mode only versions that existed for the disassembler. Move the patterns out of the instructions so they can still be qualified with predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225157 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 08:19:12 +00:00
Craig Topper
34f96b9cc3 [X86] Simplify code a little by just summing flags instead of conditionally incrementing. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225156 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 08:19:10 +00:00