Commit Graph

32842 Commits

Author SHA1 Message Date
Hans Wennborg
f082c5b27f Revert r231324 "Remove the conditional addition of the execution dependency fixing"
See PR22799.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231348 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-05 03:24:49 +00:00
Eric Christopher
061096482f Remove the conditional addition of the execution dependency fixing
pass from the ARM backend as the pass itself will detect any use
of the appropriate register class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231324 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-05 00:28:55 +00:00
Eric Christopher
b56d7b0316 Cleanup and remove a chunk of getARMSubtarget calls in the
ARM TargetMachine pass pipeline construction by pushing them down
into the appropriate pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231323 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-05 00:23:40 +00:00
Nemanja Ivanovic
b69d556c37 Add LLVM support for PPC cryptography builtins
Review: http://reviews.llvm.org/D7955


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231285 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-04 20:44:33 +00:00
Mehdi Amini
c94da20917 Make DataLayout Non-Optional in the Module
Summary:
DataLayout keeps the string used for its creation.

As a side effect it is no longer needed in the Module.
This is "almost" NFC, the string is no longer
canonicalized, you can't rely on two "equals" DataLayout
having the same string returned by getStringRepresentation().

Get rid of DataLayoutPass: the DataLayout is in the Module

The DataLayout is "per-module", let's enforce this by not
duplicating it more than necessary.
One more step toward non-optionality of the DataLayout in the
module.

Make DataLayout Non-Optional in the Module

Module->getDataLayout() will never returns nullptr anymore.

Reviewers: echristo

Subscribers: resistor, llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D7992

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231270 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-04 18:43:29 +00:00
Marek Olsak
506d4b2cb4 R600/SI: Add an intrinsic for S_FLBIT_I32 / V_FFBH_I32
Required by OpenGL (ARB_gpu_shader5).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231259 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-04 17:33:45 +00:00
Nemanja Ivanovic
34173c4063 Test commit. Removed an unnecessary space
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231257 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-04 17:09:12 +00:00
JF Bastien
81338a4890 Mutate TargetLowering::shouldExpandAtomicRMWInIR to specifically dictate how AtomicRMWInsts are expanded.
Summary:
In PNaCl, most atomic instructions have their own @llvm.nacl.atomic.* function, each one, with a few exceptions, represents a consistent behaviour across all NaCl-supported targets. Unfortunately, the atomic RMW operations nand, [u]min, and [u]max aren't directly represented by any such @llvm.nacl.atomic.* function. This patch refines shouldExpandAtomicRMWInIR in TargetLowering so that a future `Le32TargetLowering` class can selectively inform the caller how the target desires the atomic RMW instruction to be expanded (ie via load-linked/store-conditional for ARM/AArch64, via cmpxchg for X86/others?, or not at all for Mips) if at all.

This does not represent a behavioural change and as such no tests were added.

Patch by: Richard Diamond.

Reviewers: jfb

Reviewed By: jfb

Subscribers: jfb, aemerson, t.p.northover, llvm-commits

Differential Revision: http://reviews.llvm.org/D7713

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231250 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-04 15:47:57 +00:00
Jozef Kolek
2e37a6f306 [mips][microMIPS] Make usage of ADDU16 and SUBU16 by code generator
Differential Revision: http://reviews.llvm.org/D7609


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231249 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-04 15:47:42 +00:00
Bill Schmidt
a558232f85 [PowerPC] Remove unnecessary and incomplete commentary
This "itinerary class map" in PPCSchedule.td is incomplete and
redundant with the actual code.  As it provides no value, we've
decided to remove it.

No functional change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231246 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-04 14:56:05 +00:00
Andrea Di Biagio
da5e5688e9 [X86][FastISel] Simplify the logic in method X86SelectSIToFP.
The target-independent selection algorithm in FastISel already knows how
to select a SINT_TO_FP if the target is SSE but not AVX.

On targets that have SSE but not AVX, the tablegen'd 'fastEmit' functions
for ISD::SINT_TO_FP know how to select instruction X86::CVTSI2SSrr
(for an i32 to f32 conversion) and X86::CVTSI2SDrr (for an i32 to f64
conversion).

This patch simplifies the logic in method X86SelectSIToFP knowing that
the code would not be reachable if the subtarget doesn't have AVX.
No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231243 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-04 14:23:25 +00:00
Toma Tabacu
dee2f990fe [mips] Rename the LA/LI/DLI TableGen definitions and classes. NFC.
Summary:
Use more reasonable names for these pseudo-instructions.
As there's only one definition tied to any one of these classes, I named them with abbreviated versions of their respective class' name.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7831

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231240 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-04 13:01:14 +00:00
Vasileios Kalintiris
2a817f81d2 [mips] Keep the parameter list of Filler::searchRange() consistent. NFC.
Summary:
Move the "Filler" parameter to the end of the parameter list as it is,
conceptually, the only output parameter of that function.

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7726

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231239 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-04 12:37:58 +00:00
Vasileios Kalintiris
ab4d9a3b38 [mips] Specify the correct value type when combining a CMovFP node.
This commit fixes a bug introduced in r230956 where we were creating
CMovFP_{T,F} nodes with multiple return value types (one for each operand).
With this change the return value type of the new node is the same as the
value type of the True/False operands of the original node.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231237 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-04 12:10:18 +00:00
Kristof Beyls
78c4ef5120 Fix PR22408 - LLVM producing AArch64 TLS relocations that GNU linkers cannot handle yet.
As is described at http://llvm.org/bugs/show_bug.cgi?id=22408, the GNU linkers
ld.bfd and ld.gold currently only support a subset of the whole range of AArch64
ELF TLS relocations. Furthermore, they assume that some of the code sequences to
access thread-local variables are produced in a very specific sequence.
When the sequence is not as the linker expects, it can silently mis-relaxe/mis-optimize
the instructions.
Even if that wouldn't be the case, it's good to produce the exact sequence,
as that ensures that linkers can perform optimizing relaxations.

This patch:

* implements support for 16MiB TLS area size instead of 4GiB TLS area size. Ideally clang
  would grow an -mtls-size option to allow support for both, but that's not part of this patch.
* by default doesn't produce local dynamic access patterns, as even modern ld.bfd and ld.gold
  linkers do not support the associated relocations. An option (-aarch64-elf-ldtls-generation)
  is added to enable generation of local dynamic code sequence, but is off by default.
* makes sure that the exact expected code sequence for local dynamic and general dynamic
  accesses is produced, by making use of a new pseudo instruction. The patch also removes
  two (AArch64ISD::TLSDESC_BLR, AArch64ISD::TLSDESC_CALL) pre-existing AArch64-specific pseudo
  SDNode instructions that are superseded by the new one (TLSDESC_CALLSEQ).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231227 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-04 09:12:08 +00:00
Davide Italiano
8667ab752e [MC][Target] Implement support for R_X86_64_SIZE{32,64}.
Differential Revision:	D7990
Reviewed by:	rafael, majnemer


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231216 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-04 06:49:39 +00:00
Pete Cooper
05be9b1a5e Remove MCStreamer.h include from MCContext.h and explictly include it where necessary. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231193 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-04 01:24:11 +00:00
Juergen Ributzka
e49da9aff1 Remove 'llvm.x86.avx2.vbroadcasti128' intrinsic.
The intrinsic is no longer generated by the front-end. Remove the intrinsic and
auto-upgrade it to a vector shuffle.

Reviewed by Nadav

This is related to rdar://problem/18742778.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231182 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-04 00:13:25 +00:00
Eric Christopher
0e5fc6e238 Remove subtarget dependence in pass pipeline setup for AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231165 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-03 23:22:40 +00:00
David Blaikie
5f4b9f892b Avoid copying LiveInterval, this could lead to a double-delete
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231154 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-03 22:25:48 +00:00
David Blaikie
317ccafdbd Revert "Remove the explicit SDNodeIterator::operator= in favor of the implicit default"
Accidentally committed a few more of these cleanup changes than
intended. Still breaking these out & tidying them up.

This reverts commit r231135.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231136 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-03 21:18:16 +00:00
David Blaikie
b13215ec3b Remove the explicit SDNodeIterator::operator= in favor of the implicit default
There doesn't seem to be any need to assert that iterator assignment is
between iterators over the same node - if you want to reuse an iterator
variable to iterate another node, that's perfectly acceptable. Just
don't mix comparisons between iterators into disjoint sequences, as
usual.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231135 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-03 21:17:08 +00:00
Paul Robinson
1f8fa31e5d [X86][ELF] Correct relocation for DWARF TLS references
Previously we had only Linux using DTPOFF for these; all X86 ELF
targets should. Fixes a side issue mentioned in PR21077.

Differential Revision: http://reviews.llvm.org/D8011


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231130 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-03 21:01:27 +00:00
Sanjay Patel
4549d733da remove enum value names from comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231129 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-03 20:58:35 +00:00
Sanjay Patel
d885b861e6 use bool operator shortcut; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231123 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-03 20:41:27 +00:00
Kit Barton
40057e8ee8 Add the following 64-bit vector integer arithmetic instructions added in POWER8:
vaddudm
vsubudm
vmulesw
vmulosw
vmuleuw
vmulouw
vmuluwm
vmaxsd
vmaxud
vminsd
vminud
vcmpequd
vcmpequd.
vcmpgtsd
vcmpgtsd.
vcmpgtud
vcmpgtud.
vrld
vsld
vsrd
vsrad

Phabricator review: http://reviews.llvm.org/D7959


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231115 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-03 19:55:45 +00:00
Eric Christopher
b900a6d000 80-column fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231088 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-03 17:54:39 +00:00
Chad Rosier
f1de1adc82 [AArch64] When combining constant mul of -3, prefer (sub x, (shl x, N)).
This change only effects codegen when the constant is -3.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231085 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-03 17:31:01 +00:00
Michael Kuperstein
822a753804 [X86][Haswell][SchedModel] Fix patterns for scalar FMA3 variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231073 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-03 15:47:02 +00:00
Elena Demikhovsky
ae765411fc AVX-512: Moved patterns for masked load/store under avx_store, avx_load classes.
No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231069 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-03 15:03:35 +00:00
Craig Topper
fc2c7a558b [X86] Remove some unused code from disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231055 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-03 05:24:03 +00:00
Ahmed Bougacha
14593eb417 [X86] Special-case 2x CMOV when custom-inserting.
This lets us avoid a few copies that are otherwise hard to get rid of.
The way this is done is, the custom-inserter looks at the following
instruction for another CMOV, and replaces both at the same time.
A previous version used a new CMOV2 opcode, but the custom inserter
is expected to be able to return a different basic block anyway, which
means it's OK - though far from ideal - to alter that block's contents.
Explicitly document that, in case it ever makes a difference.
Alternatives welcome!

Follow-up to r231045.

rdar://19767934
Closes http://reviews.llvm.org/D8019


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231046 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-03 01:21:16 +00:00
Ahmed Bougacha
8b5527deef [X86] Combine (cmov (and/or (setcc) (setcc))) into (cmov (cmov)).
Fold and/or of setcc's to double CMOV:

(CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
(CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)

When we can't use the CMOV instruction, it might increase branch
mispredicts.  When we can, or when there is no mispredict, this
improves throughput and reduces register pressure.

These can't be catched by generic combines, because the pattern can
appear when legalizing some instructions (such as fcmp une).

rdar://19767934
http://reviews.llvm.org/D7634


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231045 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-03 01:09:14 +00:00
Paul Robinson
7f9bc0986b Remove useless .debug_macinfo section setup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231001 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-02 19:52:42 +00:00
Jan Vesely
e8676a29bb R600: Use c++11 style for loop
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <tom@stellard.net>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230987 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-02 18:56:52 +00:00
Paul Robinson
a2541bd006 Revert r230979, should apply to all X86 ELF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230985 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-02 18:50:18 +00:00
Paul Robinson
d31f89ebc1 [PS4] Correct relocation for DWARF TLS references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230979 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-02 17:44:52 +00:00
Elena Demikhovsky
53fb369429 AVX-512: Add assembly parser support for Rounding mode
By Asaf Badouh <asaf.badouh@intel.com>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230962 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-02 15:00:34 +00:00
Benjamin Kramer
c5a15087c2 NVPTX: Remove dead code.
Fun fact: This file was never referenced since the initial checkin of
the NVPTX backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230957 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-02 13:16:28 +00:00
Vasileios Kalintiris
5a393cab69 [mips] Optimize conditional moves where RHS is zero.
Summary:
When the RHS of a conditional move node is zero, we can utilize the $zero
register by inverting the conditional move instruction and by swapping the
order of its True/False operands.

Reviewers: dsanders

Differential Revision: http://reviews.llvm.org/D7945

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230956 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-02 12:47:32 +00:00
Elena Demikhovsky
e206743835 AVX-512: Simplified MOV patterns, no functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230954 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-02 12:46:21 +00:00
Craig Topper
2d9a799b16 [X86] There are only 8 mask registers. Fail disassembly if instruction tries to reference more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230931 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-02 03:33:11 +00:00
Craig Topper
a2d7ca4495 [X86] Fix diassembler crash on AVX512 cmpps/cmppd with immediate that doesn't fit in 5-bits. Fixes PR22743.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230924 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-02 00:22:29 +00:00
Sanjoy Das
6e125c1adb [AArch64] fix an invalid-iterator-use bug.
Summary:
In AArch64PromoteConstant::appendAndTransferDominatedUses,
`InsertPts[NewPt]` invalidates IPI.  Therefore, `InsertPts[NewPt] =
std::move(IPI->second)` is not legal.

This was caught by running `make check` with
http://reviews.llvm.org/D7931.

Reviewers: t.p.northover, grosbach, bkramer

Reviewed By: bkramer

Subscribers: aemerson, llvm-commits

Differential Revision: http://reviews.llvm.org/D7988

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230923 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-02 00:17:18 +00:00
Benjamin Kramer
adad988089 X86: Replace variadic function with init list. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230911 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-01 21:47:40 +00:00
Benjamin Kramer
c255d35a10 ArrayRef: Remove the equals helper with many arguments.
With initializer lists there is a really neat idiomatic way to write
this, 'ArrayRef.equals({1, 2, 3, 4, 5})'. Remove the equal method which
always had a hard limit on the number of arguments. I considered
rewriting it with variadic templates but that's not really a good fit
for a function with homogeneous arguments.

'ArrayRef == {1, 2, 3, 4, 5}' would've been even more awesome, but C++11
doesn't allow init lists with binary operators.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230907 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-01 21:05:05 +00:00
Benjamin Kramer
30fa873958 Make some non-constant static variables non-static or fully const.
Otherwise we have to emit thread-safe initialization for them. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230894 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-01 18:09:56 +00:00
Elena Demikhovsky
bf4d9a8aaf Reverted 230471 - gather scatter handling in table gen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230892 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-01 08:23:41 +00:00
Elena Demikhovsky
975e9b99aa AVX-512: Added mask and rounding mode for scalar arithmetics
Added more tests for scalar instructions to destinguish between AVX and AVX-512 forms.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230891 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-01 07:44:04 +00:00
Craig Topper
8df1c6ef09 [X86] Remove the blendpd/blendps/pblendw/pblendd intrinsics. They can represented by shuffle_vector instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230860 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-28 19:33:17 +00:00