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f0efafa61e
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5970 Commits

Author SHA1 Message Date
Rafael Espindola
f0efafa61e wip 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106408 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 02:17:34 +00:00
Nick Lewycky
2a3ee5e8e9 Fix warning in no-asserts build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106405 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-20 20:27:42 +00:00
Bruno Cardoso Lopes
f6ff003043 Refactoring of regular logical packed instructions to prepare for AVX ones. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106375 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 04:09:22 +00:00
Bruno Cardoso Lopes
f4f4bad696 Refactor aliased packed logical instructions, also add 
AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106374 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 02:44:01 +00:00
Bruno Cardoso Lopes
1e8d06282f Move new sse 1 & 2 generic classes to a more appropriate place 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106372 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 01:32:46 +00:00
Bruno Cardoso Lopes
efc9b69deb Remove unnecessary arguments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106371 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 01:22:34 +00:00
Bruno Cardoso Lopes
17227db062 Add AVX packed intrinsics for MIN, MAX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106370 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 01:17:05 +00:00
Eric Christopher
a938cfb13a Finish ripping isTwoAddress out of X86. Some mindless formatting 
and operand renaming to help.

The giant turn the constraints on and selectively turn it off
should probably be inverted at some point since it's just largely
50/50.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106367 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:37:40 +00:00
Bruno Cardoso Lopes
be4d595afd Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106366 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:37:31 +00:00
Chris Lattner
617e595022 rip out dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106365 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:34:14 +00:00
Chris Lattner
1cf44fc051 fix rdar://7873482 by teaching the instruction encoder to emit 
segment prefixes.  Daniel wrote most of this patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106364 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:34:00 +00:00
Bruno Cardoso Lopes
fda1acb389 Clean up: remove now unnecessary Constraints 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106361 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:09:27 +00:00
Bruno Cardoso Lopes
c82f199892 more refactoring! yay! big win over the intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106359 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:00:22 +00:00
Eric Christopher
96ab7f494d Remove isTwoAddress from here too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106358 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:56:07 +00:00
Bruno Cardoso Lopes
ccf30bd984 Fix typo, SSE1 should be used by XS, not SSE2 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106357 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:53:27 +00:00
Eric Christopher
f6bc0b9d4b Remove isTwoAddress from 64-bit files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106356 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:51:21 +00:00
Dan Gohman
db4971259c Teach regular and fast isel to set dead flags on unused implicit defs 
on calls and similar instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106353 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:28:01 +00:00
Bruno Cardoso Lopes
8af5ed9e15 Apply some refactor to packed instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106349 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:13:35 +00:00
Bruno Cardoso Lopes
4b8921d1c7 Use the new 'defm' class inheritance in SSE 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106327 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 22:10:11 +00:00
Dan Gohman
1415a602ad Make this comment less specific. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106311 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 20:45:41 +00:00
Dan Gohman
ea9f151cbc Fix X86FastISel's address-mode folding to stay within the 
original basic block. This avoids trouble with examining
instructions in other basic blocks which haven't been
assigned registers yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106310 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 20:44:47 +00:00
Dan Gohman
027657db7c Change UpdateNodeOperands' operand and return value from SDValue to 
SDNode *, since it doesn't care about the ResNo value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106282 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 15:30:29 +00:00
Dan Gohman
5ff12fc41a Delete unused variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106280 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 14:32:32 +00:00
Dan Gohman
e368b460a2 Eliminate unnecessary uses of getZExtValue(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106279 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 14:22:04 +00:00
Dan Gohman
7720cb3823 isValueValidForType can be a static member function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106278 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 14:01:07 +00:00
Eric Christopher
f627dc37bf Some assorted isTwoAddress -> Constraints cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106273 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 02:41:19 +00:00
Dan Gohman
e54081088e Don't maintain a set of deleted nodes; instead, use a HandleSDNode 
to track a node over CSE events. This fixes PR7368.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106266 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 01:24:29 +00:00
Bruno Cardoso Lopes
d7f9cc4de7 Add {mix,max}{ss,sd}{rr,rm} AVX forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106264 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 01:12:56 +00:00
Dan Gohman
8a7f7426ee Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass, 
which is faster, simpler, and less surprising.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106263 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 01:05:21 +00:00
Bruno Cardoso Lopes
597ec8ed51 Use new tablegen resources in SSE tablegen code. This will 
be done incrementally and intermixed with the adding of more
AVX instructions. This is a first step in that direction


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106251 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 23:05:30 +00:00
Stuart Hastings
3bf9125933 Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This 
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 22:43:56 +00:00
Eric Christopher
e98ad83543 Hack to let the move lowering handle dynamic-no-pic absolute moves of 
TLVP:

movl _a@TLVP, %eax

Daniel: Please review if you get a chance.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106194 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 00:51:48 +00:00
Bill Wendling
d361a77f14 Create a more targeted fix for not sinking instructions into a range where it 
will conflict with another live range. The place which creates this scenerio is
the code in X86 that lowers a select instruction by splitting the MBBs. This
eliminates the need to check from the bottom up in an MBB for live pregs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106066 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 23:46:31 +00:00
Eric Christopher
6102549737 For 32-bit non-pic tlv mach-o addressing we don't need a pic base or 
a relative address.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106064 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 23:08:42 +00:00
Dale Johannesen
bf37850e42 Reapply 105986 with fix for bug pointed out by Jakob: 
flag argument to addReg is not the same format as flags attached
to MachineOperand, although both have the same info.  I don't
think this actually mattered; the bootstrap failure did not
reproduce on the next run anyway.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106049 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 21:36:43 +00:00
Chris Lattner
868ee9460c fix fastisel to handle GS and FS relative pointers. Patch by 
Nelson Elhage!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106031 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 19:08:40 +00:00
Dale Johannesen
69ba5c6aa8 Revert 105986; looks like I'd better try bootstrapping. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105988 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 04:55:06 +00:00
Dale Johannesen
4b559f070a The form of BuildMI used for TAILJMPr was changing the register 
containing the target address, an input, into an output.  I don't
think this actually broke anything on x86 (it does on ARM), but
it's wrong.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105986 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 03:13:49 +00:00
Chris Lattner
6b601536ff fix a nasty bug where we were not treating available_externally 
symbols as declarations in the X86 backend.  This would manifest
on darwin x86-32 as errors like this with -fvisibility=hidden:

symbol '__ZNSbIcED1Ev' can not be undefined in a subtraction expression

This fixes PR7353.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105954 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-14 20:11:56 +00:00
Eli Friedman
e103194851 Add back some possible optimizations for va_arg, with wording that makes it 
more clear what exactly is missing.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105934 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-14 07:03:30 +00:00
Rafael Espindola
21d238fdba Merge getStoreRegOpcode and getLoadRegOpcode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105900 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-12 20:13:29 +00:00
Bruno Cardoso Lopes
2dcf6d6019 make the avx intrinsics 3 address 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105876 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-12 03:12:14 +00:00
Bruno Cardoso Lopes
11ae95c175 Add some basic fp intrinsics for AVX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105873 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-12 02:38:32 +00:00
Bruno Cardoso Lopes
cf125d02a0 More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rm 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105870 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-12 01:53:48 +00:00
Bruno Cardoso Lopes
7be0d2c8e9 More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rr 
Handle OpSize TSFlag for AVX



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105869 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-12 01:23:26 +00:00
Bruno Cardoso Lopes
e4f6907a7a Add some comments about REX fields 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105860 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-12 00:03:52 +00:00
Bruno Cardoso Lopes
c902a59f4c More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm) 
Introduce the VEX_X field


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105859 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-11 23:50:47 +00:00
Eli Friedman
092f9c116a A few new x86-64 specific README entries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105674 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-09 02:43:17 +00:00
Kevin Enderby
09712b57ce Incremental improvement to the handling of the x86 "Jump if rCX Zero" 
instruction.  Added the 64-bit version "jrcxz" so it is recognized and also
added the checks for incorrect uses of "jcxz" in 64-bit mode and "jrcxz" in
32-bit mode.  Still to do is to correctly handle the encoding of the
instruction adding the Address-size override prefix byte, 0x67, when the width
of the count register is not the same as the mode the machine is running in.
Which for example means the encoding of "jecxz" depends if you are assembling
as a 32-bit target or a 64-bit target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105661 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-08 23:48:44 +00:00
Eric Christopher
497f1eb2b8 Split out these asserts so it's more apparent why we're not assembling 
that rip-relative address when executing in 32-bit mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105656 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-08 22:57:33 +00:00