Commit Graph

13 Commits

Author SHA1 Message Date
Matt Arsenault
507c5af818 R600: Cleanup fneg tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214612 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-02 02:26:51 +00:00
Tom Stellard
17c8fefc9f R600/SI: Do abs/neg folding with ComplexPatterns
Abs/neg folding has moved out of foldOperands and into the instruction
selection phase using complex patterns.  As a consequence of this
change, we now prefer to select the 64-bit encoding for most
instructions and the modifier operands have been dropped from
integer VOP3 instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214467 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 00:32:39 +00:00
Vincent Lejeune
e283f74133 R600/SI: Fold fabs/fneg into src input modifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208480 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-10 19:18:39 +00:00
Vincent Lejeune
3378ca7d5c R600/SI: Prettier display of input modifiers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208479 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-10 19:18:33 +00:00
Michel Danzer
de2e0bc366 R600/SI: Fix fneg for 0.0
V_ADD_F32 with source modifier does not produce -0.0 for this. Just
manipulate the sign bit directly instead.

Also add a pattern for (fneg (fabs ...)).

Fixes a bunch of bit encoding piglit tests with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200743 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-04 07:12:38 +00:00
Tom Stellard
b52bf6a3b3 R600/SI: Prefer SALU instructions for bit shift operations
All shift operations will be selected as SALU instructions and then
if necessary lowered to VALU instructions in the SIFixSGPRCopies pass.

This allows us to do more operations on the SALU which will improve
performance and is also required for implementing private memory
using indirect addressing, since the private memory pointers must stay
in the scalar registers.

This patch includes some fixes from Matt Arsenault.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194625 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 23:36:37 +00:00
Matt Arsenault
86245071b5 R600/SI: Change formatting of printed registers.
Print the range of registers used with a single letter prefix.
This better matches what the shader compiler produces and
is overall less obnoxious than concatenating all of the
subregister names together.

Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1,
it will print s[0:1] and so on.

There doesn't appear to be a straightforward way
to get the actual register info in the InstPrinter,
so this parses the generated name to print with the
new syntax.

The required test changes are pretty nasty, and register
matching regexes are now worse. Since there isn't a way to
add to a variable in FileCheck, some of the tests now don't
check the exact number of registers used, but I don't think that
will be a real problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194443 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 02:35:51 +00:00
Tom Stellard
f9e5c39811 R600/SI: Use S_LOAD_DWORD instructions for v8i32 and v16i32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193212 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-23 00:44:12 +00:00
Vincent Lejeune
bb25a01d23 R600: Non vector only instruction can be scheduled on trans unit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189980 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-04 19:53:46 +00:00
Tom Stellard
6b3f6a744a Revert "R600: Non vector only instruction can be scheduled on trans unit"
This reverts commit 98ce62780e.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187526 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 20:43:27 +00:00
Vincent Lejeune
98ce62780e R600: Non vector only instruction can be scheduled on trans unit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187514 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 19:31:56 +00:00
Tom Stellard
1f67c63cb2 DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)Free
This commit also implements these functions for R600 and removes a test
case that was relying on the buggy behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187007 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 23:55:03 +00:00
Tom Stellard
d7a472c9c6 R600: Expand vector FNEG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186913 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 01:47:46 +00:00