Commit Graph

96245 Commits

Author SHA1 Message Date
Daniel Sanders
f1ef27e6e3 [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191498 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 10:08:31 +00:00
Daniel Sanders
d2a31a124f [mips][msa] Expand all truncstores and loadexts for MSA as well as DSP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191496 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 09:44:59 +00:00
Daniel Sanders
86f309b4d1 [mips][msa] Added missing check in performSRACombine
Reviewers: jacksprat, dsanders

Reviewed By: dsanders

Differential Revision: http://llvm-reviews.chandlerc.com/D1755

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191495 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 09:25:29 +00:00
Puyan Lotfi
6b4fa2256c First check in. Modified a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191491 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 07:36:10 +00:00
Craig Topper
62f6fac1c5 Put HasAVX512 predicate on some patterns to properly disable them when AVX512 isn't enabled. Currently it works simply because the SSE and AVX version of the same patterns are checked first in the DAG isel table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191490 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 07:20:47 +00:00
Craig Topper
1f31a3794e Switch HasAVX to UseAVX in one spot to ensure that AVX512 form of VINSERTPS is used in AVX512 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191489 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 07:16:24 +00:00
Craig Topper
11989c2685 Removal some duplicate patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191488 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 07:11:17 +00:00
Yunzhong Gao
d7f5fac111 Fixing Intel format of the vshufpd instruction.
Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191481 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 01:44:23 +00:00
Rui Ueyama
4715a11dcf Revert "llvm-objdump: Dump COFF import table if -private-headers option is given."
This reverts commit r191472 because it's failing on BE machine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191480 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 01:29:36 +00:00
Rui Ueyama
10965f2045 Fix another -Wnon-pod-varargs error in r191472.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191474 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 00:53:07 +00:00
Rui Ueyama
2f00626f7e Fix -Wnon-pod-varargs error in r191472.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191473 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 00:20:53 +00:00
Rui Ueyama
0c873adc82 llvm-objdump: Dump COFF import table if -private-headers option is given.
This is a patch to add capability to llvm-objdump to dump COFF Import Table
entries, so that we can write tests for LLD checking Import Table contents.

llvm-objdump did not print anything but just file name if the format is COFF
and -private-headers option is given. This is a patch adds capability for
dumping DLL Import Table, which is specific to the COFF format.

In this patch I defined a new iterator to iterate over import table entries.
Also added a few functions to COFFObjectFile.cpp to access fields of the entry.

Differential Revision: http://llvm-reviews.chandlerc.com/D1719

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191472 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 00:07:01 +00:00
Adrian Prantl
deac137da7 MCParser/Debug info: Accept line number 0 as a legitimate value, since
CFE produces it to indicate artificial locations.
c.f.: DWARF standard, Table 6.2:
line -- An unsigned integer indicating a source line number. Lines are numbered beginning at 1. The compiler may emit the value 0 in cases where an instruction cannot be attributed to any source line.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191471 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 23:37:11 +00:00
Jack Carter
1327c08922 [mips][msa] Direct Object Emission for 3RF instructions.
Patch by Matheus Almeida


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191461 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 21:31:43 +00:00
Jack Carter
00a5b53e14 [mips][msa] Updates encoding of 3RF instructions to match the latest revision of the MSA spec (1.06).
This does not affect any of the existing output.

Patch by Matheus Almeida


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191460 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 21:18:57 +00:00
Weiming Zhao
82f36241c2 Fix PR 17372: Emitting PLD for stack address for ARM Thumb2
t2PLDi12, t2PLDi8, t2PLDs was omitted in Thumb2InstrInfo.
This patch fixes it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191441 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 17:25:10 +00:00
Bill Schmidt
daf6b948b9 [PowerPC] Fix PR17354: Generate nop after local calls for PIC code.
When generating code for shared libraries, even local calls may be
intercepted, so we need a nop after the call for the linker to fix up the
TOC.  Test case adapted from the one provided in PR17354.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191440 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 17:09:28 +00:00
Andrea Di Biagio
6c73cf5a8a Revert r191393 since it caused pr17380.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191438 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 16:54:01 +00:00
Venkatraman Govindaraju
30ec8a3658 [Sparc] Implements exception handling in SPARC with DwarfCFI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191432 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 15:11:00 +00:00
Venkatraman Govindaraju
83ba58e5f0 Implements parsing and emitting of .cfi_window_save in MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191431 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 14:49:40 +00:00
Amara Emerson
268c743a3b [ARM] Use the load-acquire/store-release instructions optimally in AArch32.
Patch by Artyom Skrobov.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191428 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 12:22:36 +00:00
David Majnemer
9637da6083 PPC: Allow partial fills in writeNopData()
When asked to pad an irregular number of bytes, we should fill with
zeros.  This is consistent with the behavior specified in the AIX
Assembler Language Reference as well as other LLVM and binutils
assemblers.

N.B. There is a small deviation from binutils' PPC assembler:
when handling pads which are greater than 4 bytes but not mod 4,
binutils will not emit any NOP sequences at all and only use zeros.
This may or may not be a bug but there is no excellent rationale as to
why that behavior is important to emulate.  If that behavior is needed,
we can change writeNopData() to behave in the same way.

This fixes PR17352.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191426 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 09:18:48 +00:00
Renato Golin
6b4e9ba218 Add links to cross-compilation docs from getting started
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191425 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 08:57:07 +00:00
Andrew Trick
b6ac11cd03 Added temp flag -misched-bench for staging in default changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191423 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 05:53:35 +00:00
Andrew Trick
7394a7c0c2 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191422 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 05:53:31 +00:00
David Majnemer
dd5cebdd74 PPC: Do not introduce ISD nodes for fctid and fctiw
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191421 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 05:22:11 +00:00
David Majnemer
11c2b15c0a PPC: Add support for fctid and fctiw
Encodings were checked against the Power ISA documents and double
checked against binutils.

This fixes PR17350.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191419 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 04:11:24 +00:00
Jack Carter
9fa81ab838 [mips][msa] Direct Object Emission for 3R instructions.
This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class.
 
Patch by Matheus Almeida


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191415 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 00:09:46 +00:00
Jack Carter
afee613bf3 [mips][msa] Updates encoding of 3R instructions to match the latest revision of the MSA spec (1.06).
Internal changes only.
 
Patch by Matheus Almeida


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191414 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 00:02:44 +00:00
Jack Carter
4167b88cf5 [mips][msa] Direct Object Emission for 2RF instructions.
Patch by Matheus Almeida


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 23:56:25 +00:00
Jack Carter
42d9ca6299 [mips][msa] Direct Object Emission support for the MSA instruction set.
In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions.

Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function).

Patch by Matheus Almeida


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191412 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 23:50:44 +00:00
Jack Carter
825e5583b6 [mips][msa] Updates encoding of 2RF instructions to match the latest revision of the MSA spec (1.06).
This only changes internal encodings and doesn't affect output.


Patch by Matheus Almeida


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191411 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 23:42:03 +00:00
Weiming Zhao
541681c848 Fix PR 17368: disable vector mul distribution for square of add/sub for ARM
Generally, it is desirable to distribute (a + b) * c to a*c + b*c for
ARM with VMLx forwarding, where a, b and c are vectors.
However, for (a + b)*(a + b), distribution will result in one extra
instruction.
With distribution:
  x = a + b (add)
  y = a * x (mul)
  z = y + b * y (mla)

Without distribution:
  x = a + b (add)
  z = x * x (mul)

This patch checks if a mul is a square of add/sub. If yes, skip
distribution.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191410 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 23:12:06 +00:00
Eric Christopher
498ffb8a56 Add gnu pubsections as options to llvm-dwarfdump.
Argument spelling feedback welcome.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191409 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 23:02:44 +00:00
Eric Christopher
7357f03e88 Dump the normal dwarf pubtypes section as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191408 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 23:02:41 +00:00
Eric Christopher
c839df0e4c Unify pubsection/gnu pubsection printing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191407 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 23:02:36 +00:00
Josh Magee
4e1c4d69e4 Test commit. Removed trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191402 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 22:07:48 +00:00
Eric Christopher
f8809477be Slight formatting change for pubnames/pubtypes output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191401 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 21:17:37 +00:00
Reed Kotler
55d016886c Fix a bad typo in the inline assembly code for mips16 pic fp stubs
and make one cosmetic cleanup to make it look the same as gcc
in this area; adjusting test cases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191400 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 20:58:50 +00:00
Andrea Di Biagio
2ce3ac8dd8 Teach DAGCombiner how to canonicalize dags according to the rule
(shl (zext (shr A, X)), X) => (zext (shl (shr A, X), X)).

The rule only triggers when there are no other uses of the
zext to avoid materializing more instructions.

This helps the DAGCombiner understand that the shl/shr
sequence can then be converted into an and instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191393 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 19:01:01 +00:00
Andrew Trick
0701564377 Mark the x86 machine model as incomplete. PR17367.
Ideally, the machinel model is added at the time the instructions are
defined. But many instructions in X86InstrSSE.td still need a model.

Without this workaround the scheduler asserts because x86 already has
itinerary classes for these instructions, indicating they should be
modeled by the scheduler. Since we use the new machine model for other
instructions, it expects a new machine model for these too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191391 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 18:14:12 +00:00
Joerg Sonnenberger
2558c2bfba Undefine NetBSD, it may have been defined by an earlier include of
sys/param.h.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191384 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 17:49:57 +00:00
Rafael Espindola
19c450af62 Set the minimal stack size with msvc when using cmake >= 2.8.11.
This makes sure we get the same behavior with all supported cmake versions. Once
we support only versions >= 2.8.11 we can experiment with other values or just
setting it for some binaries.

Patch by Greg Bedwell.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191372 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 14:06:55 +00:00
Arnold Schwaighofer
9660ebb398 SLPVectorize: Put horizontal reductions feeding a store under separate flag
Put them under a separate flag for experimentation. They are more likely to
interfere with loop vectorization which happens later in the pass pipeline.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191371 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 14:02:32 +00:00
Richard Sandiford
259a6006e8 [SystemZ] Define the GR64 low-word logic instructions as pseudo aliases.
Another patch to avoid duplication of encoding information.  Things like
NILF, NILL and NILH are used as both 32-bit and 64-bit instructions.
Here the 64-bit versions are defined as aliases of the 32-bit ones.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191369 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 11:11:53 +00:00
David Majnemer
3f22cc1df6 MC: Add support for treating $ as a reference to the PC
The binutils assembler supports a mode called DOLLAR_DOT which treats
the dollar sign token as a reference to the current program counter if
the dollar sign doesn't precede a constant or identifier.

This commit adds a new MCAsmInfo flag stating whether or not a given
target supports this interpretation of the dollar sign token; by
default, this flag is not enabled.

Further, enable this flag for PPC. The system assembler for AIX and
binutils both support using the dollar sign in this manner.

This fixes PR17353.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191368 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 10:47:21 +00:00
Richard Sandiford
76f8ae87b4 [SystemZ] Define the call instructions as pseudo aliases.
Similar to r191364, but for calls.  This patch also removes the shortening
of BRASL to BRAS within a TU.  Doing that was a bit controversial internally,
since there's a strong expectation with the z assembler that WYWIWYG.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 10:37:17 +00:00
Richard Sandiford
e39a156b92 [SystemZ] Use subregs for 64-bit truncating stores
Another patch to reduce the duplication of encoding information.
Rather than define separate patterns for truncating 64-bit stores,
use the 32-bit stores with a subreg.  No behavioral changed intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191365 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 10:29:47 +00:00
Richard Sandiford
9f3f4bf377 [SystemZ] Define the return instruction as a pseudo alias of BR
This is the first of a few patches to reduce the dupliation of encoding
information.  The return instruction is a normal BR in which one of the
registers is fixed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191364 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 10:20:08 +00:00
Richard Sandiford
c2b840cb7c [SystemZ] Add instruction-shortening pass
When loading immediates into a GR32, the port prefered LHI, followed by
LLILH or LLILL, followed by IILF.  LHI and IILF are natural 32-bit
operations, but LLILH and LLILL also clear the upper 32 bits of the register.
This was represented as taking a 32-bit subreg of a 64-bit assignment.

Using subregs for something as simple as a move immediate was probably
a bad idea.  Also, I have patches to add support for the high-word facility, 
and we don't want something like LLILH and LLILL to stop the high word of
the same GPR from being used.

This patch therefore uses LHI and IILF to begin with and adds a late
machine-specific pass to use LLILH and LLILL if the other half of the
register is not live.  The high-word patches extend this behavior to
IIHF, LLIHL and LLIHH.

No behavioral change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191363 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 10:11:07 +00:00