Commit Graph

80032 Commits

Author SHA1 Message Date
Andrew Trick
f1f78d5266 Initialize all common codegen passes before configuration so we can use their PassIDs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149705 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 20:14:47 +00:00
Chad Rosier
36b7beb429 [fast-isel] Add support for selecting UIToFP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149704 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 19:42:52 +00:00
Duncan Sands
b95d1ff437 Simplify some GEP checks in the verifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149698 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 17:28:51 +00:00
Nadav Rotem
7e413e9c94 The type-legalizer often scalarizes code. One of the common patterns is extract-and-truncate.
In this patch we optimize this pattern and convert the sequence into extract op of a narrow type.
This allows the BUILD_VECTOR dag optimizations to construct efficient shuffle operations in many cases.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149692 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 13:18:25 +00:00
Craig Topper
a02556679e Remove getShuffleVPERMILPImmediate function, getShuffleSHUFImmediate performs the same calculation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149683 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 06:52:33 +00:00
Cameron Zwarich
a99350511c Allow command-line overrides of the target triple with the Mach-O
disassembler, just like the generic disassembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149681 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 06:35:22 +00:00
Craig Topper
fa5b70e1d8 Remove unnecessary qualification on 256-bit vector handling in LowerBUILD_VECTOR. Condition was already guaranteed by earlier code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149680 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 06:32:21 +00:00
Craig Topper
e058d27655 Add auto upgrade support for x86 pcmpgt/pcmpeq intrinics removed in r149367.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149678 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 06:10:55 +00:00
Cameron Zwarich
ec8eac6d8b Do the same fix as r149667, but for the Mach-O disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149674 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 05:42:17 +00:00
Andrew Trick
843ee2e6a4 Added TargetPassConfig. The first little step toward configuring codegen passes.
Allows command line overrides to be centralized in LLVMTargetMachine.cpp.
LLVMTargetMachine can intercept common passes and give precedence to command line overrides.
Allows adding "internal" target configuration options without touching TargetOptions.
Encapsulates the PassManager.
Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs.
Allows modifying the target configuration hooks without rebuilding the world.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149672 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 05:12:41 +00:00
Andrew Trick
8247e0dca6 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149671 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 05:12:30 +00:00
Akira Hatanaka
6c2cf8b1fb Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is
needed to emit a 64-bit gp-relative relocation entry. Make changes necessary
for emitting jump tables which have entries with directive .gpdword. This patch
does not implement the parts needed for direct object emission or JIT.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149668 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 04:33:00 +00:00
Cameron Zwarich
aab2191109 Fix llvm-objdump disassembly for interesting Mach-O binaries, e.g. any MacOS
dylib. This regressed with r145408. I will try to make a test case and add it
so that this doesn't happen again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149667 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 04:13:37 +00:00
Lang Hames
6e3f7e4913 Incorporate suggestions Chad, Jakob and Evan's suggestions on r149957.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 01:13:49 +00:00
Dan Gohman
16717a7c56 Fix SSAUpdaterImpl's RecordMatchingPHI to record exactly the
PHI nodes which were matched, rather than climbing up the
original PHI node's operands to rediscover PHI nodes for
recording, since the PHI nodes found that are not
necessarily part of the matched set.
This fixes rdar://10589171.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149654 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 01:07:01 +00:00
Rafael Espindola
1aee22e072 Replace the old --with-cxx-* configure options with a single --with-gcc-toolchain
that just uses the new toolchain probing logic. This fixes linking with -m32 on
64 bit systems (the /32 dir was not being added to the search).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149651 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 00:59:30 +00:00
Jim Grosbach
871a2051f7 Narrow test further. Make bot and test happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149650 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 00:26:07 +00:00
Jim Grosbach
00e403abe3 Tidy up. Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149649 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 00:07:04 +00:00
Jim Grosbach
f374486659 Restrict InstCombine from converting varargs to or from fixed args.
More targetted fix replacing d0e277d272.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149648 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 00:00:55 +00:00
Jim Grosbach
d5917f0b4d Revert "Disable InstCombine unsafe folding bitcasts of calls w/ varargs."
This reverts commit d0e277d272.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149647 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 00:00:50 +00:00
Jakob Stoklund Olesen
478a8a02bc Require non-NULL register masks.
It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 23:52:57 +00:00
Daniel Dunbar
2e5b88e3cb build/make: Ensure make clean removes the LLVMBuild makefile fragment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149643 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 23:27:34 +00:00
Daniel Dunbar
8979f4e711 build/Make: Add missing dependency, LLVMBuild makefile fragment implicitly depends on Makefile.config.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149642 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 23:27:32 +00:00
Jakob Stoklund Olesen
42865588d7 Add pseudo-registers for pairs, triples, and quads of D registers.
NEON loads and stores accept single and double spaced pairs, triples,
and quads of D registers.  This patch adds new register classes to
accurately model those constraints:

  Dn, Dn+1    Dn, Dn+2
  ----------------------
  DPair       DPairSpc
  DTriple     DTripleSpc
  DQuad       DQuadSpc

Also extend the existing QQ and QQQQ register classes to contains all Q
pairs and quads instead of just the aligned ones.

These new register classes will make it possible to accurately model
constraints on NEON loads and stores, and we can get rid of all the NEON
pseudo-instructions.  The late scheduler will be able to accurately
model instruction dependencies from the explicit operands.

This more than doubles the number of ARM registers, but the backend
passes are quite good at handling this. The llc -O0 compile time only
regresses by 1.5%.  Future work on register mask operands will recover
this regression.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149640 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 22:45:32 +00:00
Matt Beaumont-Gay
6ab8949cc1 Unix line endings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149615 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 19:00:49 +00:00
Benjamin Kramer
ded681d272 BBVectorize: Simplify code, no functionality change.
Also silences warnings about bodyless for loops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149612 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 18:52:15 +00:00
Hal Finkel
35564dc3ae Minor changes from review.
As suggested by Nick Lewycky, the tree traversal queues have been changed to SmallVectors and the associated loops have been rotated. Also, an 80-col violation was fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149607 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 17:29:39 +00:00
NAKAMURA Takumi
7a73925c50 Move test/CodeGen/Generic/2012-02-01-CoalescerBug.ll to CodeGen/ARM, for now. It requires TARGETS=arm.
I cannot reproduce a fixed issue with other targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149604 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 11:44:58 +00:00
Elena Demikhovsky
0f1ead47a0 Minor change in signature of the getZeroVector()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149601 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 09:20:18 +00:00
Elena Demikhovsky
dcabc7bca9 Optimization for SIGN_EXTEND operation on AVX.
Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32
extensions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149600 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 09:10:43 +00:00
Francois Pichet
1ae52f686c Unbreak the MSVC build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149599 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 08:36:09 +00:00
Lang Hames
eec68e7ffa Re-apply the coalescer fix from r149147. Commit r149597 should have fixed the llvm-gcc and clang self-host issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149598 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 08:01:53 +00:00
Lang Hames
50a36f7102 Set EFLAGS correctly in EmitLoweredSelect on X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149597 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 07:48:37 +00:00
Lang Hames
d88710a3e0 Break as soon as the MustMapCurValNos flag is set - no need to reiterate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149596 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 06:55:45 +00:00
Hal Finkel
5d4e18bc39 Vectorize long blocks in groups.
Long basic blocks with many candidate pairs (such as in the SHA implementation in Perl 5.14; thanks to Roman Divacky for the example) used to take an unacceptably-long time to compile. Instead, break long blocks into groups so that no group has too many candidate pairs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149595 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 06:14:56 +00:00
Lang Hames
02e08d5b4d PR11868. The previous loop in LiveIntervals::join would sometimes fall over if
more than two adjacent ranges needed to be merged. The new version should be
able to handle an arbitrary sequence of adjancent ranges.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149588 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 05:37:34 +00:00
Akira Hatanaka
3f5b107a4b Set the correct stack pointer register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149585 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 03:17:04 +00:00
Akira Hatanaka
590baca06c Expand EHSELECTION and EHSELECTION nodes. Set the correct exception pointer and
selector registers.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149584 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 03:13:40 +00:00
Akira Hatanaka
1ad175e7e0 Add DWARF numbers of 64-bit registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149583 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 02:56:14 +00:00
Eric Christopher
9b3cd4890d Regen one last time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149576 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 01:11:30 +00:00
Dylan Noblesmith
32cf80bd01 autoconf: fix build/src dir confusion
This was the cause of the silent failure to generate
clang's config.h. My bad.

Fix on r149563 / r149568.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149574 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 00:54:18 +00:00
Eric Christopher
ac89865faf Regenerate again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149569 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 00:19:05 +00:00
Dylan Noblesmith
db6caea4f8 autoconf: restore old clang-srcdir behavior
Keep the string empty when unspecified. Undoes
part of r149563.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149568 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 00:17:33 +00:00
Eric Christopher
63c0951999 Regenerate configure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149567 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 00:16:55 +00:00
Dylan Noblesmith
8d6dd0f807 autoconf: honor --with-clang-srcdir
configure was silently failing to produce anything in the case
where clang wasn't at tools/clang/, resulting in compilation
errors much later in the build when config.h didn't exist.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149563 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 00:11:14 +00:00
Pete Cooper
af39368988 Typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149562 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01 23:43:12 +00:00
Rafael Espindola
6ac40af2de Fix the cmake build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149561 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01 23:40:51 +00:00
Andrew Trick
922d314e8f Instruction scheduling itinerary for Intel Atom.
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.

Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.

Adds a test to verify that the scheduler is working.

Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.

Patch by Preston Gurd!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01 23:20:51 +00:00
Jakob Stoklund Olesen
521804a1f7 Move ARM subreg index compositions to the SubRegIndex itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149557 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01 23:16:43 +00:00
Jakob Stoklund Olesen
b5af2d943e Specify SubRegIndex components on the index itself.
It is simpler to define a composite index directly:

  def ssub_2 : SubRegIndex<[dsub_1, ssub_0]>;
  def ssub_3 : SubRegIndex<[dsub_1, ssub_1]>;

Than specifying the composite indices on each register:

  CompositeIndices = [(ssub_2 dsub_1, ssub_0),
                      (ssub_3 dsub_1, ssub_1)] in ...

This also makes it clear that SubRegIndex composition is supposed to be
unique.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01 23:16:41 +00:00