Commit Graph

11359 Commits

Author SHA1 Message Date
Chris Lattner
f4b284f991 chase owen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118124 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 23:55:24 +00:00
Chris Lattner
ca99597ed5 tweak this to pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118122 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 23:50:17 +00:00
Chris Lattner
d5b02302f3 temporarily xfail this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 23:44:50 +00:00
John Thompson
45c21ff044 Inline asm mult-alt constraint tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118107 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 23:01:44 +00:00
Bill Wendling
5df0e0a61d Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:31:46 +00:00
Owen Anderson
b20594fce6 Provide correct encodings for the remaining vst variants that we currently generate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118087 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:18:18 +00:00
Owen Anderson
a1a45fd254 Add correct encodings for basic variants for vst3 and vst4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118082 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 21:47:03 +00:00
Owen Anderson
d2f3794e4d Add correct encodings for the basic variants for vst2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118068 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 21:16:58 +00:00
Owen Anderson
cfebe3a8b1 Add correct encodings for the basic form of vst1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 21:06:06 +00:00
Owen Anderson
f0ea0f2b15 Add correct encodings for the rest of the vld instructions that we generate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118053 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 20:40:59 +00:00
Jim Grosbach
ab3d00e535 Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke
assumptions about stack layout. Specifically, LR must be saved next to FP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118026 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 17:35:25 +00:00
Rafael Espindola
3ff57094a7 Add support for expressions in .sleb/.uleb directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118023 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 17:22:24 +00:00
Devang Patel
a90b305af9 Use frameindex, if available, as a last resort to emit debug info for a parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118020 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 17:01:30 +00:00
Owen Anderson
cf667be17b Add correct NEON encodings for vld2, vld3, and vld4 basic variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117997 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 01:24:55 +00:00
Owen Anderson
d9aa7d30aa Add correct NEON encodings for the "multiple single elements" form of vld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 00:05:05 +00:00
Bob Wilson
665814b6be Add support for alignment operands on VLD1-lane instructions.
This is another part of the fix for Radar 8599955.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117976 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 23:40:51 +00:00
Bob Wilson
baf0615426 Add VLD1-lane testcases for quad-register types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117975 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 23:40:46 +00:00
Bob Wilson
b796bbb6de Add NEON VLD1-lane instructions. Partial fix for Radar 8599955.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117964 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 22:04:05 +00:00
Bill Wendling
933b314c76 Use ARM-style comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
Owen Anderson
648b20d5db When folding away a (shl (shr)) pair, we need to check that the bits that will BECOME the low
bits are zero, not that the current low bits are zero.  Fixes <rdar://problem/8606771>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117953 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:08:20 +00:00
Bill Wendling
40a5eb18b0 When we look at instructions to convert to setting the 's' flag, we need to look
at more than those which define CPSR. You can have this situation:

(1)  subs  ...
(2)  sub   r6, r5, r4
(3)  movge ...
(4)  cmp   r6, 0
(5)  movge ...

We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:

(1)  sub   r1, r2, r3
(2)  sub   r4, r5, r6
(3)  cmp   r4, ...
(5)  movge ...
(6)  cmp   r1, ...
(7)  movge ...

We cannot convert (1) to "subs" because of the intervening use of CPSR.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117950 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 20:41:43 +00:00
Owen Anderson
95b9766fea Use ARM-style comment syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 18:33:37 +00:00
Bob Wilson
24645a1a6d NEON does not support truncating vector stores. Radar 8598391.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117940 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 18:31:39 +00:00
Owen Anderson
4845f99008 Covert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117939 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 18:30:39 +00:00
Owen Anderson
60b75fad7e Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 18:26:43 +00:00
Owen Anderson
3b5dfcd8fd Covert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117937 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 18:13:11 +00:00
Owen Anderson
2bcb989a0b Covert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117935 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 18:03:16 +00:00
Rafael Espindola
d1d73b03af Fix test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117932 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 17:10:53 +00:00
Rafael Espindola
c70a1d985a Write the line info to .debug_line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117930 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 17:07:14 +00:00
Jim Grosbach
833c93c795 Mark ARM subtarget features that are available for the assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117929 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 16:59:54 +00:00
Rafael Espindola
cc3acee7b3 Add support for .value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117922 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 15:29:07 +00:00
Rafael Espindola
484291c273 Implement .weakref.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117911 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 14:28:48 +00:00
Bill Wendling
504fb4fb8e More tests to XFAIL. The arm-and-txt-peephole.ll test passes even when the
peephole optimizer is disabled. That's not good at all.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117905 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 05:59:43 +00:00
Bill Wendling
59707e8055 Disable because peephole is disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 05:48:44 +00:00
Chris Lattner
acc473fcf9 "mov[zs]x (mem), GR16" are not ambiguous: the mem
must be 8 bits.  Support this memory form.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117902 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 05:41:10 +00:00
Chris Lattner
b501d4f673 Implement enough of the missing instalias support to get
aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 05:34:34 +00:00
Owen Anderson
b8d14a6611 Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117900 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 05:23:58 +00:00
Chris Lattner
4164f6bbbf make the asm matcher emitter reject instructions that have comments
in their asmstring.  Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 04:44:29 +00:00
Chris Lattner
1a1ecc9f3c fix an encoding mismatch where "sal %eax, 1" was not using the short encoding
for shl.  Caught by inspection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 18:13:10 +00:00
Chris Lattner
905b8f7614 add a test for the ud2a alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117803 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 17:01:25 +00:00
Duncan Sands
ad6f541840 If a function does a volatile load from a global constant, do not
consider it to be readonly.  In fact, don't even consider it to be
readonly if it does a volatile load from an AllocaInst either (it
is debatable as to whether readonly would be correct or not in this
case; play safe for the moment).  This fixes PR8279.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117783 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 12:59:44 +00:00
Bob Wilson
f74a429816 Overhaul memory barriers in the ARM backend. Radar 8601999.
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain.  It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions.  Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions.  Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 00:54:37 +00:00
Bill Wendling
52925b60f1 Some instructions end with an "ls" prefix, but it doesn't indicate that they are
conditional. Check for those instructions explicitly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
Evan Cheng
189c1ec4c1 Teach machine cse to eliminate instructions with multiple physreg uses and defs. rdar://8610857.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:36:03 +00:00
Rafael Espindola
d179886f05 Be more strict on when we produce an undefined reference. In gas a file with
just

.type   foo,@object

will produce an undefined reference to foo. On the other hand, a file with
just

.weakref bar, foo

will not. It is somewhat hard to support both in MC since both statements
should create the symbols. It should be possible if we really need to by
adding to the flags, but hopefully that is not necessary.

With this patch we do not produce a undefined reference in any of those cases.
The assembly file needs an actual use for the undefined reference to be
present.

This is in preparation for a patch implementing .weakref.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117735 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:09:31 +00:00
Bob Wilson
822cb58d08 Change instcombine's getShuffleMask to represent undef with negative values.
This code had previously used 2*N, where N is the mask length, to represent
undef.  That is not safe because the shufflevector operands may have more
than N elements -- they don't have to match the result type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117721 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 22:03:05 +00:00
Bob Wilson
46455096be Remove DAG combiner patch to fold vector splats. Instcombiner does it now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 22:03:02 +00:00
Bob Wilson
4cac5facc3 Make instcombine a little more aggressive in combining vector shuffles.
Allow splats even if they don't match either of the original shuffles,
possibly due to undef entries in the shuffles masks.  Radar 8597790.
Also fix some 80-column violations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117719 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 22:02:50 +00:00
Owen Anderson
b20955f319 Update testcase since we're no longer doing the constant forwarding inline with correlated value propagation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117712 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 21:18:23 +00:00
Owen Anderson
05cee0cdb4 Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117708 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 20:39:19 +00:00