Commit Graph

3176 Commits

Author SHA1 Message Date
Ulrich Weigand
d999062f31 Handle tied sub-operands in AsmMatcherEmitter
The problem this patch addresses is the handling of register tie
constraints in AsmMatcherEmitter, where one operand is tied to a
sub-operand of another operand.  The typical scenario for this to
happen is the tie between the "write-back" register of a pre-inc
instruction, and the base register sub-operand of the memory address
operand of that instruction.

The current AsmMatcherEmitter code attempts to handle tied
operands by emitting the operand as usual first, and emitting
a CVT_Tied node when handling the second (tied) operand.  However,
this really only works correctly if the tied operand does not
have sub-operands (and isn't a sub-operand itself).  Under those
circumstances, a wrong MC operand list is generated.

In discussions with Jim Grosbach, it turned out that the MC operand
list really ought not to contain tied operands in the first place;
instead, it ought to consist of exactly those operands that are
named in the AsmString.  However, getting there requires significant
rework of (some) targets.

This patch fixes the immediate problem, and at the same time makes
one (small) step in the direction of the long-term solution, by
implementing two changes:

1. Restricts the AsmMatcherEmitter handling of tied operands to
   apply solely to simple operands (not complex operands or
   sub-operand of such).

This means that at least we don't get silently corrupt MC operand
lists as output.  However, if we do have tied sub-operands, they
would now no longer be handled at all, except for:

2. If we have an operand that does not occur in the AsmString,
   and also isn't handled as tied operand, simply emit a dummy
   MC operand (constant 0).

This works as long as target code never attempts to access
MC operands that do no not occur in the AsmString (and are
not tied simple operands), which happens to be the case for
all targets where this situation can occur (ARM and PowerPC).

[ Note that this change means that many of the ARM custom
  converters are now superfluous, since the implement the
  same "hack" now performed already by common code. ]

Longer term, we ought to fix targets to never access *any*
MC operand that does not occur in the AsmString (including
tied simple operands), and then finally completely remove
all such operands from the MC operand list.

Patch approved by Jim Grosbach.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180677 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-27 18:48:23 +00:00
Andrew Trick
a809c8db3d Machine model: Generate table entries for super-resources.
Super-resources and resource groups are two ways of expressing
overlapping sets of processor resources. Now we generate table entries
the same way for both so the scheduler never needs to explicitly check
for super-resources.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180162 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23 23:45:16 +00:00
Andrew Trick
e30f32a69b Machine model: verify well-formed processor resource groups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180161 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23 23:45:14 +00:00
Andrew Trick
6982bdd119 Machine model: rewrite a tablegen loop to avoid comparing record pointers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180160 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23 23:45:11 +00:00
Chad Rosier
88eb89b89f [asm parser] Add support for predicating MnemonicAlias based on the assembler
variant/dialect.  Addresses a FIXME in the emitMnemonicAliases function.
Use and test case to come shortly.
rdar://13688439 and part of PR13340.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179804 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18 22:35:36 +00:00
Michael Liao
02d2e61252 Add CLAC/STAC instruction encoding/decoding support
As these two instructions in AVX extension are privileged instructions for
special purpose, it's only expected to be used in inlined assembly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11 04:52:28 +00:00
Andrew Trick
bc4de7cec1 Fix TableGen subtarget-emitter to handle A9/Swift.
A9 uses itinerary classes, Swift uses RW lists. This tripped some
verification when we're expanding variants. I had to refine the
verification a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178357 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 19:08:31 +00:00
Dan Gohman
1cbd401756 Revert r178166. According to Howard, this code is actually ok.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178319 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 00:13:08 +00:00
Dan Gohman
dcdc0faf59 Avoid undefined behavior from passing a std::vector's own contents
in as an argument to push_back.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178166 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27 18:44:56 +00:00
Andrew Trick
82e7c4f533 TableGen SubtargetEmitter fix to allow A9 and Swift to coexist.
Allow variants to be defined only for some processors on a target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178074 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26 21:36:39 +00:00
Dave Zarzycki
9b3939983f x86 -- add the XTEST instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177888 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 18:59:43 +00:00
Jakob Stoklund Olesen
8e3cb3ee0c Allow types to be omitted in output patterns.
This syntax is now preferred:

  def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>;

There is no reason to repeat the types in the output pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177844 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24 19:37:00 +00:00
Jakob Stoklund Olesen
19209960b6 Allow direct value types to be used in instruction 'set' patterns.
This makes it possible to define instruction patterns like this:

def LDri : F3_2<3, 0b000000,
                (outs IntRegs:$dst), (ins MEMri:$addr),
                "ld [$addr], $dst",
                [(set i32:$dst, (load ADDRri:$addr))]>;
                      ~~~

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177834 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24 00:56:16 +00:00
Jakob Stoklund Olesen
f0a804df49 Allow direct value types in pattern definitions.
Just like register classes, value types can be used in two ways in
patterns:

  (sext_inreg i32:$src, i16)

In a named leaf node like i32:$src, the value type simply provides the
type of the node directly. This simplifies type inference a lot compared
to the current practice of specifiying types indirectly with register
classes.

As an unnamed leaf node, like i16 above, the value type represents
itself as an MVT::Other immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177828 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23 20:35:01 +00:00
Jakob Stoklund Olesen
7a42fb3b6e Make all unnamed RegisterClass TreePatternNodes typed MVT::i32.
A register class can appear as a leaf TreePatternNode with and without a
name:

  (COPY_TO_REGCLASS GPR:$src, F8RC)

In a named leaf node like GPR:$src, the register class provides type
information for the named variable represented by the node. The TypeSet
for such a node is the set of value types that the register class can
represent.

In an unnamed leaf node like F8RC above, the register class represents
itself as a kind of immediate. Such a node has the type MVT::i32,
we'll never create a virtual register representing it.

This change makes it possible to remove the special handling of
COPY_TO_REGCLASS in CodeGenDAGPatterns.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177825 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23 18:08:44 +00:00
Sean Silva
426db657da Add TableGen ctags(1) emitter and helper script.
To use this in conjunction with exuberant ctags to generate a single
combined tags file, run tblgen first and then
  $ ctags --append [...]

Since some identifiers have corresponding definitions in C++ code,
it can be useful (if using vim) to also use cscope, and
  :set cscopetagorder=1
so that
  :tag X
will preferentially select the tablegen symbol, while
  :cscope find g X
will always find the C++ symbol.

Patch by Kevin Schoedel!

(a couple small formatting changes courtesy of clang-format)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177682 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-21 23:40:38 +00:00
Ulrich Weigand
ec8d1a5b72 Extend TableGen instruction selection matcher to improve handling
of complex instruction operands (e.g. address modes).

Currently, if a Pat pattern creates an instruction that has a complex
operand (i.e. one that consists of multiple sub-operands at the MI
level), this operand must match a ComplexPattern DAG pattern with the
correct number of output operands.

This commit extends TableGen to alternatively allow match a complex
operands against multiple separate operands at the DAG level.

This allows using Pat patterns to match pre-increment nodes like
pre_store (which must have separate operands at the DAG level) onto
an instruction pattern that uses a multi-operand memory operand,
like the following example on PowerPC (will be committed as a
follow-on patch):

  def STWU  : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst),
                    "stwu $rS, $dst", LdStStoreUpd, []>,
                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;

  def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff),
            (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>;

Here, the pair of "ptroff" and "ptrreg" operands is matched onto the
complex operand "dst" of class "memri" in the "STWU" instruction.

Approved by Jakob Stoklund Olesen.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177428 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19 19:51:09 +00:00
Andrew Trick
02fec34de1 TableGen fix for the new machine model.
Properly handle cases where a group of instructions have different
SchedRW lists with the same itinerary class.
This was supposed to work, but I left in an early break.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177317 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18 20:42:25 +00:00
Jakob Stoklund Olesen
4c16916883 Extract a method.
This computes the type of an instruction operand or result based on the
records in the instruction's ins and outs lists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177244 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18 04:08:07 +00:00
Jakob Stoklund Olesen
26369a930c Use ArrayRef<MVT::SimpleValueType> when possible.
Not passing vector references around makes it possible to use
SmallVector in most places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177235 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-17 17:26:09 +00:00
Andrew Trick
1ab961f6d3 Machine model. Allow mixed itinerary classes and SchedRW lists.
We always supported a mixture of the old itinerary model and new
per-operand model, but it required a level of indirection to map
itinerary classes to SchedRW lists. This was done for ARM A9.

Now we want to define x86 SchedRW lists, with the goal of removing its
itinerary classes, but still support the itineraries in the mean
time. When I original developed the model, Atom did not have
itineraries, so there was no reason to expect this requirement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177226 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-16 18:58:55 +00:00
Jakob Stoklund Olesen
64110ffc9e Add SchedRW as an Instruction field.
Don't require instructions to inherit Sched<...>. Sometimes it is more
convenient to say:

  let SchedRW = ... in {
    ...
  }

Which is now possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177199 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15 22:51:13 +00:00
Andrew Trick
157c6c4e8e Fix r177112: Add ProcResGroup.
This is the other half of r177122 that I meant to commit at the same time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 22:47:01 +00:00
Andrew Trick
1754aca83a MachineModel: Add a ProcResGroup class.
This allows abitrary groups of processor resources. Using something in
a subset automatically counts againts the superset. Currently, this
only works if the superset is also a ProcResGroup as opposed to a
SuperUnit.

This allows SandyBridge to be expressed naturally, which will be
checked in shortly.

def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>;
def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>;
def SBPort23  : ProcResGroup<[SBPort2, SBPort3]>;
def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177112 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 21:21:50 +00:00
Kevin Enderby
12dccaed9c Fixes disassembler crashes on 2013 Haswell RTM instructions.
rdar://13318048


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176828 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11 21:17:13 +00:00
Andrew Trick
c812110023 MIsched machine model: tablegen subtarget emitter improvement.
Fix the way resources are counted. I'm taking some time to cleanup the
way MachineScheduler handles in-order machine resources. Eventually
we'll need more PPC/Atom test cases in tree.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176390 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01 23:31:26 +00:00
Michael J. Spencer
f15fe8195b [TableGen] Fix ICE on MSVC 2012 Release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176125 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-26 21:29:47 +00:00
Jyotsna Verma
1912c7624a Fix for bug 15246 -- out-of-bound error in the TableGen backend, CodeGenMapTable.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175185 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 17:58:13 +00:00
David Peixotto
af7c042af1 PR14992 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIA
Fixed bug in tablegen conversion when source pseudo instruction has
a different number of arguments than the destination instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175066 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 19:21:47 +00:00
Kay Tiong Khoo
6c3daabc3e Added 0x0D to 2-byte opcode extension table for prefetch* variants
Fixed decode of existing 3dNow prefetchw instruction
Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174920 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12 00:19:12 +00:00
Jim Grosbach
fa05def52c Allow targets to add custom asm operand matching logic.
For example, ARM has several instructions with a literal '#0' immediate in the syntax
that's not represented as an actual operand. The asm matcher is expected a token
operand, but the parser will have created an immediate operand. This is currently
handled by dedicated per-instruction C++ munging of the ParsedAsmOperand list, but
will be better handled by this hook.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174487 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06 06:00:06 +00:00
Eli Bendersky
d07c2a5fa1 Fix comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174390 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 16:53:11 +00:00
Jack Carter
37ef65b9c1 This patch that sets the EmitAlias flag in td files
and enables the instruction printer to print aliased 
instructions. 

Due to usage of RegisterOperands a change in common 
code (utils/TableGen/AsmWriterEmitter.cpp) is required 
to get the correct register value if it is a RegisterOperand.

Contributer: Vladimir Medic
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174358 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 08:32:10 +00:00
Andrew Trick
d9a4f0cbd2 MachineModel: Inconsequential TableGen SubtargetEmitter fix.
Drive by fix. I noticed some missing logic that might bite future
users. This shouldn't affect the final output on currently modeled
targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174142 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-01 03:19:54 +00:00
Jakob Stoklund Olesen
f79c5e2f84 Clarify intent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174068 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31 17:56:23 +00:00
Tim Northover
72062f5744 Add AArch64 as an experimental target.
This patch adds support for AArch64 (ARM's 64-bit architecture) to
LLVM in the "experimental" category. Currently, it won't be built
unless requested explicitly.

This initial commit should have support for:
    + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions
      (except the late addition CRC instructions).
    + CodeGen features required for C++03 and C99.
    + Compilation for the "small" memory model: code+static data <
      4GB.
    + Absolute and position-independent code.
    + GNU-style (i.e. "__thread") TLS.
    + Debugging information.

The principal omission, currently, is performance tuning.

This patch excludes the NEON support also reviewed due to an outbreak of
batshit insanity in our legal department. That will be committed soon bringing
the changes to precisely what has been approved.

Further reviews would be gratefully received.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31 12:12:40 +00:00
Bill Wendling
e3617247a0 Use the AttributeSet instead of AttributeWithIndex.
In the future, AttributeWithIndex won't be used anymore. Besides, it exposes the
internals of the AttributeSet to outside users, which isn't goodness.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173606 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27 03:25:05 +00:00
Chad Rosier
1c99a7f489 [ms-inline asm] Address the FIXME in AsmParser.cpp.
// FIXME: Constraints are hard coded to 'm', but we need an 'r'
// constraint for addressof.  This needs to be cleaned up!

Test cases are already in place.  Specifically,
clang/test/CodeGen/ms-inline-asm.c t15(), t16(), and t24().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-15 23:07:53 +00:00
Michael Ilseman
4d0b4a45dc Support for half intrinsics. Pushes MMX into slower encoding path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172159 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11 01:45:05 +00:00
Jordan Rose
b50df4a3df TableGen: Keep track of superclass reference ranges.
def foo : bar;
          ~~~

This allows us to produce more precise diagnostics about a certain
superclass, and even provide fixits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172085 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10 18:50:11 +00:00
Tim Northover
12da505d93 Remove locale-dependence of enum mangling and use existing function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172077 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10 16:47:31 +00:00
Tim Northover
88abcde3b4 Make TableGen mangle operand method names before putting in enum.
The purpose of this patch is to allow PredicateMethods to be set to something
like "isUImm<8>", calling a C++ template method to reduce code duplication. For
this to work, the PredicateMethod must be mangled into a valid C++ identifier
for insertion into an enum.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172073 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10 15:17:36 +00:00
Tim Northover
7bf2e1b9ef Check whether MCInst operand isImm before calling getImm.
When processing possible aliases, TableGen assumes that if an operand *can* be
an immediate, then it always *will* be. This is incorrect for the AArch64
backend. This patch inserts a check in the generated code to make sure isImm is
true first.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171972 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 13:32:04 +00:00
Andrew Trick
47579cf390 MIsched: add an ILP window property to machine model.
This was an experimental option, but needs to be defined
per-target. e.g. PPC A2 needs to aggressively hide latency.

I converted some in-order scheduling tests to A2. Hal is working on
more test cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171946 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 03:36:49 +00:00
Chandler Carruth
7f00f87767 Sort a few more #include lines in tools/... unittests/... and utils/...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171363 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02 10:26:28 +00:00
NAKAMURA Takumi
fc093def2d TableGen/FixedLenDecoderEmitter.cpp: Fix a potential mask overflow in fieldFromInstruction().
Reported by Yang Yongyong, thanks!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171101 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 06:43:14 +00:00
Elena Demikhovsky
94d7ab7da4 Added 6 more value types: v32i1, v64i1, v32i16, v32i8, v64i8, v8f64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171026 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-24 10:03:57 +00:00
Bill Wendling
629fb82419 Change 'AttrVal' to 'AttrKind' to better reflect that it's a kind of attribute instead of the value of the attribute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170972 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-22 00:37:52 +00:00
Richard Smith
8efd0f00be Fix an uninitialized member variable, found by -fsanitize=bool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170627 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 01:05:39 +00:00
Jim Grosbach
fbf3b4a076 MC: Add MCInstrDesc::mayAffectControlFlow() method.
MC disassembler clients (LLDB) are interested in querying if an
instruction may affect control flow other than by virtue of being
an explicit branch instruction. For example, instructions which
write directly to the PC on some architectures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170610 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 23:38:53 +00:00