Dan Gohman
a552878508
Make Solve check its own post-condition, to reduce clutter in the
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top-level LSRInstance logic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104278 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:59:23 +00:00
Dan Gohman
76c315a26c
Add comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:52:00 +00:00
Daniel Dunbar
4e7f8390c0
MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104275 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:36:29 +00:00
Devang Patel
6ed0ce3240
Rename variable. add comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104274 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:35:24 +00:00
Dan Gohman
402d43529c
More code cleanups. Use iterators instead of indices when indices
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aren't needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104273 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:33:18 +00:00
Daniel Dunbar
1fe591da3e
X86: Model i64i32imm properly, as a subclass of all immediates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104272 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:20:39 +00:00
Daniel Dunbar
0306e3ddbf
X86: Fix immediate type of FOO64i32 operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104271 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:20:35 +00:00
Daniel Dunbar
4072886a69
tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor
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it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104270 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:20:32 +00:00
Dan Gohman
c6519f916b
Fix OptimizeShadowIV to set Changed. Change OptimizeLoopTermCond to set
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Changed directly instead of using a return value.
Rename FilterOutUndesirableDedicatedRegisters's Changed variable to
distinguish it from LSRInstance's Changed member.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104269 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:05:31 +00:00
Dan Gohman
f7ff37d674
Add some comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104268 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:00:41 +00:00
Dan Gohman
d974a0e9d6
Simplify this code. Don't do a DomTreeNode lookup for each visited block.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104267 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:00:25 +00:00
Devang Patel
ee43286ca9
Refactor.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104265 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 19:57:06 +00:00
Matt Fleming
ab3b3651ad
Grammar fix. This is a test commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104264 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 19:45:09 +00:00
Dan Gohman
ea507f5c28
Minor code cleanups.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104263 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 19:44:23 +00:00
Dan Gohman
f182b23f8f
When canonicalizing icmp operand order to put the loop invariant
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operand on the left, the interesting operand is on the right. This
fixes a bug where LSR was failing to recognize ICmpZero uses,
which led it to be unable to reverse the induction variable in the
attached testcase.
Delete test/CodeGen/X86/stack-color-with-reg-2.ll, because its test
is extremely fragile and hard to meaningfully update.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104262 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 19:26:52 +00:00
Mikhail Glushenkov
eb0971529d
llvmc: Make segfault detection work on Win32.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104261 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 19:23:47 +00:00
Dan Gohman
9da1bf4845
Set Changed to true when canonicalizing ICmp operand order; even though
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it isn't a very interesting change, it's a change nonetheless.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104260 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 19:16:03 +00:00
Bob Wilson
63b8845e78
Handle Neon v2f64 and v2i64 vector shuffles as register copies.
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This fixes the remaining issue with pr7167.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104257 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 18:39:53 +00:00
Jim Grosbach
76526f8863
Remove dbg_value workaround and associated command line option
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104254 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 18:34:01 +00:00
Dan Gohman
53e184980d
Delete MMX_MOVQ64gmr. It was the same as MMX_MOVQ64mr, but it didn't
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have a pattern and it had an invalid encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104244 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 18:05:01 +00:00
Dale Johannesen
5f07d5224d
The PPC MFCR instruction implicitly uses all 8 of the CR
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registers. Currently it is not so marked, which leads to
VCMPEQ instructions that feed into it getting deleted.
If it is so marked, local RA complains about this sequence:
vreg = MCRF CR0
MFCR <kill of whatever preg got assigned to vreg>
All current uses of this instruction are only interested in
one of the 8 CR registers, so redefine MFCR to be a normal
unary instruction with a CR input (which is emitted only as
a comment). That avoids all problems. 7739628.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104238 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 17:48:26 +00:00
Devang Patel
69b4d1caff
Strip llvm.dbg.lv also.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104236 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 16:49:22 +00:00
Dan Gohman
24a7c30822
Rename a variable to avoid shadowing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104234 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 16:41:11 +00:00
Devang Patel
26c1e56f13
Split DbgVariable. Eventually, variable info will be communicated through frame index, or DBG_VALUE instruction, or collection of DBG_VALUE instructions. Plus each DbgVariable may not need a label.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 16:36:41 +00:00
Dan Gohman
4766744072
Minor code simplification.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104232 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 16:23:28 +00:00
Dan Gohman
e5e4ff974d
Fix assembly parsing and encoding of the pushf and popf family of
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104231 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 16:16:00 +00:00
Dan Gohman
100804f494
Set neverHasSideEffects on 64-bit pushf and popf, for consistency with
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16-bit and 32-bit pushf and popf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104228 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 15:42:55 +00:00
Dan Gohman
5ce6d05ad6
Move the code for deleting BaseRegs and LSRUses into helper functions,
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and fix a bug that valgrind noticed where the code would std::swap an
element with itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104225 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 15:17:54 +00:00
Benjamin Kramer
c37791e875
Reduce string trashing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104223 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 14:14:22 +00:00
Evan Cheng
15a16def6e
Add a hybrid bottom up scheduler that reduce register usage while avoiding
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pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104216 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 06:13:19 +00:00
Nick Lewycky
761fd4c1d9
Fix typo in comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104209 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 03:30:09 +00:00
Dan Gohman
14aaeac5cf
Define the x86 pause instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 01:35:50 +00:00
Dan Gohman
ee5673b622
Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it
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doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104203 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 01:23:41 +00:00
Eric Christopher
51f5d6af8c
Fix build by actually declaring the variable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 00:59:30 +00:00
Eric Christopher
c1a887d76d
Partial code for emitting thread local bss data.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104197 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 00:49:07 +00:00
Bill Wendling
ff9244a1f1
Match "4" or "8" depending upon if it's 32- or 64-bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104196 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 00:27:10 +00:00
Eric Christopher
8db52ef4b0
Once more, with feeling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104190 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 00:07:13 +00:00
Daniel Dunbar
b0ac8677fd
lit: Add another place to look for bash.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104189 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 23:56:09 +00:00
Dan Gohman
a2086b3483
Teach LSR how to cope better with unrolled loops on targets where
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the addressing modes don't make this trivially easy. This allows
it to avoid falling into the less precise heuristics in more
cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104186 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 23:43:12 +00:00
Bob Wilson
492fd454ca
Optimize away insertelement of an undef value. This shows up in
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test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code
because the coalescer cleans it up. Radar 7998853.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104185 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 23:42:58 +00:00
Chris Lattner
a7f1354eb5
fix rdar://7986634 - match instruction opcodes case insensitively.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104183 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 23:34:33 +00:00
Bill Wendling
a008750aa9
Testcase for r104181.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104182 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 23:33:26 +00:00
Jim Grosbach
de70b1f9be
Enable preserving debug information through post-RA scheduling
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104175 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 22:57:47 +00:00
Jim Grosbach
309d20c89c
Fix the post-RA instruction scheduler to handle instructions referenced by
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more than one dbg_value instruction. rdar://7759363
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104174 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 22:57:06 +00:00
Evan Cheng
e163168aab
Code clean up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104173 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 22:42:23 +00:00
Devang Patel
461a646a03
Revert r104165.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104172 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 21:58:28 +00:00
Jakob Stoklund Olesen
d32e735ae6
Add support for partial redefs to the fast register allocator.
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A partial redef now triggers a reload if required. Also don't add
<imp-def,dead> operands for physical superregisters.
Kill flags are still treated as full register kills, and <imp-use,kill> operands
are added for physical superregisters as before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 21:36:05 +00:00
Devang Patel
f4ccaeaef9
There is no need to maintain InsnsBeginScopeSet separately.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104165 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 21:26:53 +00:00
Eric Christopher
591466baff
A more combo tls testcase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104163 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 21:19:42 +00:00
Jakob Stoklund Olesen
7ebc4d63db
Add MachineInstr::readsVirtualRegister() in preparation for proper handling of
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partial redefines.
We are going to treat a partial redefine of a virtual register as a
read-modify-write:
%reg1024:6 = OP
Unless the register is fully clobbered:
%reg1024:6 = OP, %reg1024<imp-def>
MachineInstr::readsVirtualRegister() knows the difference. The first case is a
read, the second isn't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104149 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 20:36:22 +00:00