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f8e07f448a
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1626 Commits

Author SHA1 Message Date
Chris Lattner
f8e07f448a Switch loads over to use memri as the operand instead of a reg/imm operand 
pair for cleanliness.  Add instructions for PPC32 preinc-stores with commented
out patterns.  More improvement is needed to enable the patterns, but we're
getting close.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31749 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-15 02:43:19 +00:00
Chris Lattner
26e552b04c group load and store instructions together. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31736 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-14 19:19:53 +00:00
Chris Lattner
6a5339ba65 Rework PPC64 calls. Now we have a LR8/CTR8 register which the PPC64 calls 
clobber.  This allows LR8 to be save/restored correctly as a 64-bit quantity,
instead of handling it as a 32-bit quantity.  This unbreaks ppc64 codegen when
the code is actually located above the 4G boundary.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31734 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-14 18:44:47 +00:00
Chris Lattner
d10434215d remove a ton of custom selection logic no longer needed 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31733 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-14 18:43:11 +00:00
Chris Lattner
ac011bce9e lower "X = seteq Y, Z" to '(shr (ctlz (xor Y, Z)), 5)' instead of 
'(shr (ctlz (sub Y, Z)), 5)'.

The use of xor better exposes the operation to bit-twiddling logic in the
dag combiner.  For example, this:

typedef struct {
  unsigned prefix : 4;
  unsigned code : 4;
  unsigned unsigned_p : 4;
} tree_common;

int foo(tree_common *a, tree_common *b) {
  return a->code == b->code;
}

Now compiles to:

_foo:
        lwz r2, 0(r4)
        lwz r3, 0(r3)
        xor r2, r3, r2
        rlwinm r2, r2, 28, 28, 31
        cntlzw r2, r2
        srwi r3, r2, 5
        blr

instead of:

_foo:
        lbz r2, 3(r4)
        lbz r3, 3(r3)
        srwi r2, r2, 4
        srwi r3, r3, 4
        subf r2, r2, r3
        cntlzw r2, r2
        srwi r3, r2, 5
        blr

saving a cycle.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31725 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-14 05:28:08 +00:00
Chris Lattner
2fe4bf453b minor tweaks, reject vector preinc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31717 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-14 01:38:31 +00:00
Evan Cheng
7ce4578353 Matches MachineInstr changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31712 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-13 23:36:35 +00:00
Chris Lattner
c9dcf28955 teach the g5 hazard recognizer about update loads. This fixes 
Ptrdist/anagram among others.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31708 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-13 20:11:06 +00:00
Jim Laskey
dfc55885e2 Make sure stack link is set in 64-bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31690 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-11 22:22:07 +00:00
Chris Lattner
a94a203f34 implement proper PPC64 prolog/epilog codegen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31684 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-11 19:05:28 +00:00
Jim Laskey
4bfd1e9b43 Running with frame pointers prevented debugging, external probes and 
potentially some system calls/exception handling from working.  TOS must always
link to previous frame.  This is a short term workaround until alloca scheme is
reworked.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31677 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-11 10:21:58 +00:00
Chris Lattner
5b3bbc7cd7 allow the offset of a preinc'd load to be the low-part of a global. This 
produces this clever code:

_millisecs:
        lis r2, ha16(_Time.1182)
        lwzu r3, lo16(_Time.1182)(r2)
        lwz r2, 4(r2)
        addic r4, r2, 1
        addze r3, r3
        blr

instead of this:

_millisecs:
        lis r2, ha16(_Time.1182)
        la r3, lo16(_Time.1182)(r2)
        lwz r2, lo16(_Time.1182)(r2)
        lwz r3, 4(r3)
        addic r4, r3, 1
        addze r3, r2
        blr

for:

long %millisecs() {
        %tmp = load long* %Time.1182            ; <long> [#uses=1]
        %tmp1 = add long %tmp, 1                ; <long> [#uses=1]
        ret long %tmp1
}


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31673 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-11 04:53:30 +00:00
Chris Lattner
d181c0120c Mark operands as symbol lo instead of imm32 so that they print lo(x) around 
globals.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31672 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-11 04:51:36 +00:00
Chris Lattner
f6edf4dcf0 ppc64 doesn't have lwau, don't attempt to form it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31656 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-11 00:08:42 +00:00
Chris Lattner
94e509caea implement preinc support for r+i loads on ppc64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31654 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-10 23:58:45 +00:00
Chris Lattner
6a944e2592 dform 8/9 are identical to dform 1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31637 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-10 17:51:02 +00:00
Chris Lattner
4eab71497d add an initial cut at preinc loads for ppc32. This is broken for ppc64 
(because the 64-bit reg target versions aren't implemented yet), doesn't
support r+r addr modes, and doesn't handle stores, but it works otherwise. :)

This is disabled unless -enable-ppc-preinc is passed to llc for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31621 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-10 02:08:47 +00:00
Chris Lattner
26ddb506ec add note about ugly codegen with preinc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31617 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-10 01:33:53 +00:00
Evan Cheng
cd63319227 PPC supports i32 / i64 pre-inc load / store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31599 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-09 19:11:50 +00:00
Evan Cheng
144d8f09e1 Rename ISD::MemOpAddrMode to ISD::MemIndexedMode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31595 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-09 17:55:04 +00:00
Evan Cheng
0d53826f36 Match tblegen changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31571 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-08 20:34:28 +00:00
Chris Lattner
fc5b1ab949 Refactor all the addressing mode selection stuff into the isel lowering 
class, where it can be used for preinc formation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31536 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-08 02:15:41 +00:00
Chris Lattner
302bf9c973 correct the (currently unused) pattern for lwzu. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31535 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-08 02:13:12 +00:00
Chris Lattner
6e11295b23 add a note from viterbi 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31506 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-07 18:30:21 +00:00
Chris Lattner
0921365b88 fix encoding of BLR 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31485 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-07 01:51:50 +00:00
Chris Lattner
6fc40079f3 encode BLR predicate info for the JIT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31450 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-04 05:42:48 +00:00
Chris Lattner
af53a87052 Go through all kinds of trouble to mark 'blr' as having a predicate operand 
that takes a register and condition code.  Print these pieces of BLR the
right way, even though it is currently set to 'always'.

Next up: get the JIT encoding right, then enhance branch folding to produce
predicated blr for simple examples.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31449 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-04 05:27:39 +00:00
Chris Lattner
0638b260dc Describe PPC predicates, which are a pair of CR# and condition. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31438 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 23:53:25 +00:00
Chris Lattner
7049540de5 remove dead vars 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31433 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 23:46:45 +00:00
Chris Lattner
4d5c0014b6 fix a bug reid noticed 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31385 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-02 23:39:53 +00:00
Reid Spencer
3ed469ccd7 For PR786: 
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31380 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-02 20:25:50 +00:00
Chris Lattner
331d1bc5df Implement the getRegForInlineAsmConstraint method for PPC. With recent 
sdisel changes, this eliminates a ton of copies around common inline asms.
For example:

int test2(int Y, int X) {
  asm("foo %0, %1" : "=r"(X): "r"(X));
  return X;
}

now compiles to:

_test2:
        foo r3, r4
        blr

instead of:

_test2:
        mr r2, r4
        foo r2, r2
        mr r3, r2
        blr

GCC produces:

_test2:
        foo r4, r4
        mr r3,r4
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31367 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-02 01:44:04 +00:00
Chris Lattner
dba1aeedd8 Change the prototype for TargetLowering::isOperandValidForConstraint 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31318 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 19:40:43 +00:00
Anton Korobeynikov
ab4022f196 1. Clean up code due to changes in SwitchTo*Section(2) 
2. Added partial debug support for mingw\cygwin targets (the same as
   Linux\ELF). Please note, that currently mingw\cygwin uses 'stabs' format
   for storing debug info by default, thus many (runtime) libraries has
   this information included. These formats shouldn't be mixed in one binary
   ('stabs' & 'DWARF'), otherwise binutils tools will be confused.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31311 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 08:31:24 +00:00
Chris Lattner
1d75400e2e fix miscompilation of llvm.isunordered, where we branched on the opposite 
condition.  This fixes miscompilation of Olden/bh and many others.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31301 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-30 23:02:25 +00:00
Evan Cheng
c35497fc2a All targets expand BR_JT for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31294 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-30 08:02:39 +00:00
Chris Lattner
ef13982aa7 implement the BlockHasNoFallThrough hook 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31264 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-28 17:35:02 +00:00
Evan Cheng
31b6ddad31 Doh. Must check if GV is constant first before putting it in .cstring. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31253 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-28 05:56:51 +00:00
Chris Lattner
985384c41d don't dist internal readme's 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31246 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-28 00:49:54 +00:00
Chris Lattner
7a498cbc60 this doesn't occur any more in mason 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31236 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-27 22:02:19 +00:00
Chris Lattner
4ccf63d8cf the code in question is now: 
cmpw cr0, r7, r3
        ble cr0, LBB1_5 ;bb25
LBB1_8: ;bb17
        cmpw cr0, r8, r5
        bgt cr0, LBB1_2 ;bb

which is just as good as crnand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31235 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-27 22:00:55 +00:00
Evan Cheng
80aa9a122f Place cstrings in .cstring section. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31207 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-26 21:48:57 +00:00
Devang Patel
f9c197e022 Move getPreferredAlignmentLog from AsmPrinter to TargetData 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31171 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-24 20:32:14 +00:00
Chris Lattner
e90c53756e Add intrinsics for the rest of the DCB* instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31148 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-24 01:08:42 +00:00
Chris Lattner
7c4fe259f8 Implement support for branch reversal, fix a bug in branch analysis. 
This provides stuff like:

        cmpw cr0, r15, r29
        mr r14, r15
-       bge cr0, LBB3_111       ;bb656
-       b LBB3_90       ;bb501
+       blt cr0, LBB3_90        ;bb501
 LBB3_111:      ;bb656
        lwz r18, 68(r1)

which is particularly good for dispatch group formation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31101 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-21 06:03:11 +00:00
Chris Lattner
879d09cf13 Simplify code, no functionality change 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31097 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-21 05:42:09 +00:00
Chris Lattner
54108068b7 implement support for inserting a cond branch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31096 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-21 05:36:13 +00:00
Chris Lattner
10da957574 set the ppc64 stack pointer right, dynamic alloca now works for ppc64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31028 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-18 01:20:43 +00:00
Chris Lattner
56a752e00f Expand alloca for ppc64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31027 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-18 01:18:48 +00:00
Chris Lattner
ae1dc40327 expose DWARF_LABEL opcode# so the branch folder can update debug info properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31024 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-17 22:41:45 +00:00