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4218 Commits

Author SHA1 Message Date
Bill Wendling
976ef86689 During local stack slot allocation, the materializeFrameBaseRegister function 
may be called. If the entry block is empty, the insertion point iterator will be
the "end()" value. Calling ->getParent() on it (among others) causes problems.

Modify materializeFrameBaseRegister to take the machine basic block and insert
the frame base register at the beginning of that block. (It's very similar to
what the code does all ready. The only difference is that it will always insert
at the beginning of the entry block instead of after a previous materialization
of the frame base register. I doubt that that matters here.)

<rdar://problem/8782198>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122104 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-17 23:09:14 +00:00
Bob Wilson
9bb43e1675 Avoid report_fatal_error in ARM's PrintAsmOperand method. 
The standard error handling in AsmPrinter::EmitInlineAsm handles this much
better, so just use it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122100 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-17 23:06:42 +00:00
Jim Grosbach
a3dbd3a244 If The ARM WriteNopData() gets an unaligned byte count to pad out, fill in with 
a partial value. rdar://8782954

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122078 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-17 19:03:02 +00:00
Jim Grosbach
f0db261e97 Add bits 31-28 to the Thumb2 encoding of TBB/TBH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122076 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-17 18:42:56 +00:00
Jim Grosbach
6ec6eeb692 Handle 2 and 4 byte data blob fixup values for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122075 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-17 18:39:10 +00:00
Rafael Espindola
6024c97ffa Stub out explicit MCELFObjectTargetWriter interface. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122067 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-17 17:45:22 +00:00
Rafael Espindola
285b3e5b61 Move createELFObjectWriter to its own header. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122064 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-17 16:59:53 +00:00
Daniel Dunbar
1139d5090a MC/ARM: Use aggressive symbol folding (important for jump tables, for example). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122044 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-17 06:00:24 +00:00
Daniel Dunbar
7b62afac0a MC/Target: Remove HasScatteredSymbols target hook variable, which has been 
superceded and was effectively dead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122024 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-17 02:06:08 +00:00
Bob Wilson
a1f544b62e Use PairDRegs to implement ConcatVectors. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122017 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-17 01:21:08 +00:00
Jim Grosbach
3efad8fad4 Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121990 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-16 19:11:16 +00:00
Daniel Dunbar
5d05d9769e MC/Mach-O: Lift some MachObjectWriter arguments into the target specific 
interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121981 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-16 17:21:02 +00:00
Daniel Dunbar
ae5abd595f MC/Mach-O: Stub out explicit MCMachObjectTargetWriter interface. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121973 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-16 16:09:19 +00:00
Daniel Dunbar
aa4b7dd13b MC/Mach-O: Move createMachObjectWriter into MCMachObjectWriter.h. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121971 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-16 16:08:33 +00:00
Daniel Dunbar
2761fc4270 MC: Move target specific fixup info descriptors to TargetAsmBackend instead of 
the MCCodeEmitter, which seems like a better organization.
 - Also, cleaned up some magic constants while in the area.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121953 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-16 03:20:06 +00:00
Matt Beaumont-Gay
656b3d22f7 Delete an extra "Imm5 = ", caught by GCC's -Wsequence-point but not by Clang 
(see PR4579).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121939 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-16 01:34:26 +00:00
Bill Wendling
6baf46dbea Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff for 
it. I.e., it was always an immediate value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121932 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-16 00:50:33 +00:00
Bill Wendling
5a54516adf Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRi 
respectively.

It may be a bug that these opcodes are getting this far into machine code
generation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121931 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-16 00:49:54 +00:00
Bill Wendling
dedec2b89d Add encodings for Thumb1 Spill and Restore pseudos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121929 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-16 00:38:41 +00:00
Jim Grosbach
3e333637f1 Thumb1 had two patterns for the same load-from-constant-pool instruction. 
Canonicalize on tLDRpci and remove tLDRcp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121920 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 23:52:36 +00:00
Eric Christopher
836c6245ad Don't handle -arm-long-calls in fast isel for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121919 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 23:47:29 +00:00
Bill Wendling
7a905a82f7 If we're changing the frame register to a physical register other than SP, we 
need to use tLDRi and tSTRi instead of tLDRspi and tSTRspi respectively.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121915 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 23:32:27 +00:00
Bill Wendling
dc3813750e Whitespace cleanups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121914 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 23:31:24 +00:00
Bob Wilson
0406356cd4 Add Neon VCVT instructions for f32 <-> f16 conversions. 
Clang is now providing intrinsics for these and so we need to support them
in the backend.  Radar 8068427.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121902 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 22:14:12 +00:00
Jim Grosbach
d481110ef7 Tweak a few pseudo-inst pattern base classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121878 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 19:03:16 +00:00
Jim Grosbach
41b1d4e472 The new t2LEApcrel* pseudo instructions need the size specified. 
rdar://8768390

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121876 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 18:48:45 +00:00
Owen Anderson
47dbd429da Implement cleanups suggested by Daniel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121875 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 18:48:27 +00:00
Bill Wendling
22447ae54b Add fixups for Thumb LDR/STR instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121858 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 08:51:02 +00:00
Bill Wendling
bc4224bc6b Reapply r121808 now that the missing patterns have been supplied. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121820 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 01:03:19 +00:00
Bill Wendling
415af3452e Add some missing patterns now that tLDRB and tLDRH are split into reg and 
immediate versions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121819 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 00:58:57 +00:00
Bill Wendling
7d1d8db54a Revert r121808 until I can fix the build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121815 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 00:04:00 +00:00
Jim Grosbach
9d04dc52a5 thumb adr fixup needs alignment just like the t2 version. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121812 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 23:47:35 +00:00
Bill Wendling
345cdb6475 Comments and cleaning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121809 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 23:42:48 +00:00
Bill Wendling
2af0fd3fee Make the ISel selections for LDR/STR the same as before the LDRr/LDRi split. In 
particular, we want

   ldr r2, [r3]

to be equivalent to

   ldr r2, [r3, #0]

and not

   ldr r2, [r3, r0]



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121808 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 23:40:49 +00:00
Jim Grosbach
d40963c406 Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121798 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 22:28:03 +00:00
Bill Wendling
ee2b350d83 Fix comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121797 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 22:26:49 +00:00
Bill Wendling
b6faf65215 Multiclassify the LDR/STR encoding patterns. The only functionality difference 
is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121794 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 22:10:49 +00:00
Jim Grosbach
8d6d7d6e30 trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121792 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 21:28:29 +00:00
Jim Grosbach
40edf73a62 Refactor a bit for legibility. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121790 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 21:10:47 +00:00
Jim Grosbach
00f25fa43e trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121789 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 20:46:39 +00:00
Jim Grosbach
eb61272150 Make sure to propagate the predicate operands for LEApcrel to ADR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121788 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 20:45:47 +00:00
Owen Anderson
86abd48fd0 Fix a small bug (typo?) in the fixup for Thumb1 CBZ/CBNZ instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121784 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 19:42:53 +00:00
Daniel Dunbar
abfbac52df MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121772 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 17:37:16 +00:00
Jim Grosbach
e8eb1ea6ac Trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121769 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 16:25:15 +00:00
Bill Wendling
971321bb70 Use the integer scheduling intrinsic for integer loads and stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121765 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 12:33:05 +00:00
Bill Wendling
f4caf69720 The tLDR et al instructions were emitting either a reg/reg or reg/imm 
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.

The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.

There are some obvious cleanups here, which will happen shortly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121747 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 03:36:38 +00:00
Evan Cheng
0c1aec1891 bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121746 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 03:22:07 +00:00
Owen Anderson
a838a25d59 Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire 
process cleaner.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121735 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 00:36:49 +00:00
Bob Wilson
4711d5cda3 Remove the rest of the *_sfp Neon instruction patterns. 
Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now.  It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior.  Since that isn't obviously wrong, I've just
changed the test file.  This completes the work for Radar 8711675.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121730 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-13 23:02:37 +00:00
Bob Wilson
0e6d540d17 Simplify N2VSPat, removing some unnecessary type arguments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121729 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-13 23:02:31 +00:00