Commit Graph

5925 Commits

Author SHA1 Message Date
Duncan Sands
f9410141f7 Be nice to CellSPU: for this target getSetCCResultType
may return i8, which can result in SELECT nodes for
which the type of the condition is i8, but there are
no patterns for select with i8 condition.  Tweak the
LegalizeTypes logic to avoid this as much as possible.
This isn't a real fix because it is still perfectly
possible to end up with such select nodes - CellSPU
needs to be fixed IMHO.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57968 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-22 09:23:20 +00:00
Duncan Sands
29a2822f28 Port from LegalizeDAG the logic to only generate
ADDC/ADDE/SUBC/SUBE if the target supports it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57967 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-22 09:07:29 +00:00
Duncan Sands
3b521d5acc Add some comments explaining the meaning of a boolean
that is not of type MVT::i1 in SELECT and SETCC nodes.
Relax the LegalizeTypes SELECT condition promotion
sanity checks to allow other condition types than i1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57966 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-22 09:06:24 +00:00
Duncan Sands
0954aefd81 Temporarily allow the operands of a BUILD_VECTOR
to have a different type to the vector element
type.  This should be fairly harmless because in
the past guys like this were being built all over
the place (and were cleaned up when I added this
check).  The reason for relaxing this check is
that it helps LegalizeTypes legalize vector
shuffles: the mask is a BUILD_VECTOR that it is
*not always possible* to legalize while keeping it
a BUILD_VECTOR (vector_shuffle requires the mask
to be a BUILD_VECTOR, as opposed to a vector with
the right vector type).  With this check it is even
harder to legalize the mask - turning the check off
means that LegalizeTypes manages to legalize almost
all vector shuffles encountered in practice.  The
correct solution is to change vector_shuffle to be a
variadic node with the mask built into it as operands.
While waiting for that change, this hack stops the
problem with vector_shuffle from blocking the turning
on of LegalizeTypes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57965 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-22 09:00:33 +00:00
Daniel Dunbar
3b0da26e20 Move Print*Pass to use raw_ostream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57946 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-22 03:25:22 +00:00
Daniel Dunbar
f4db3a51c7 Privatize PrintModulePass and PrintFunctionPass and add
createPrintModulePass and createPrintFunctionPass.
 - So clients who compile w/o RTTI can use them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57933 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-21 23:33:38 +00:00
Dale Johannesen
1c15bf58a3 Add an SSE2 algorithm for uint64->f64 conversion.
The same one Apple gcc uses, faster.  Also gets the
extreme case in gcc.c-torture/execute/ieee/rbug.c
correct which we weren't before; this is not
sufficient to get the test to pass though, there
is another bug.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57926 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-21 20:50:01 +00:00
Dan Gohman
7ea1ca6229 Fix SelectionDAGBuild lowering of Select instructions to
handle first-class aggregate values. Also, fix a bug in
the Ret handling for empty aggregates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57925 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-21 20:00:42 +00:00
Dan Gohman
4401361a2f Don't create TargetGlobalAddress nodes with offsets that don't fit
in the 32-bit signed offset field of addresses. Even though this
may be intended, some linkers refuse to relocate code where the
relocated address computation overflows.

Also, fix the sign-extension of constant offsets to use the
actual pointer size, rather than the size of the GlobalAddress
node, which may be different, for example on x86-64 where MVT::i32
is used when the address is being fit into the 32-bit displacement
field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57885 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-21 03:38:42 +00:00
Dan Gohman
279c22e6da Optimized FCMP_OEQ and FCMP_UNE for x86.
Where previously LLVM might emit code like this:

        ucomisd %xmm1, %xmm0
        setne   %al
        setp    %cl
        orb     %al, %cl
        jne     .LBB4_2

it now emits this:

        ucomisd %xmm1, %xmm0
        jne     .LBB4_2
        jp      .LBB4_2

It has fewer instructions and uses fewer registers, but it does
have more branches. And in the case that this code is followed by
a non-fallthrough edge, it may be followed by a jmp instruction,
resulting in three branch instructions in sequence. Some effort
is made to avoid this situation.

To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and
FCMP_UNE in lowered form, and replace them with code that emits
two branches, except in the case where it would require converting
a fall-through edge to an explicit branch.

Also, X86InstrInfo.cpp's branch analysis and transform code now
knows now to handle blocks with multiple conditional branches. It
uses loops instead of having fixed checks for up to two
instructions. It can now analyze and transform code generated
from FCMP_OEQ and FCMP_UNE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57873 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-21 03:29:32 +00:00
Dan Gohman
3afda6e9d1 When the coalescer is doing rematerializing, have it remove
the copy instruction from the instruction list before asking the
target to create the new instruction. This gets the old instruction
out of the way so that it doesn't interfere with the target's
rematerialization code. In the case of x86, this helps it find
more cases where EFLAGS is not live.

Also, in the X86InstrInfo.cpp, teach isSafeToClobberEFLAGS to check
to see if it reached the end of the block after scanning each
instruction, instead of just before. This lets it notice when the
end of the block is only two instructions away, without doing any
additional scanning.

These changes allow rematerialization to clobber EFLAGS in more
cases, for example using xor instead of mov to set the return value
to zero in the included testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57872 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-21 03:24:31 +00:00
Dan Gohman
e7d238ea23 Make the NaN test come second, heuristically assuming
that NaNs are less common.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57871 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-21 03:12:54 +00:00
Oscar Fuentes
7334b15210 CMake: updated lib/CodeGen/CMakeLists.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57869 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-21 02:37:50 +00:00
Chris Lattner
01426e1a27 Fix gcc.c-torture/compile/920520-1.c by inserting bitconverts
for strange asm conditions earlier.  In this case, we have a
double being passed in an integer reg class.  Convert to like
sized integer register so that we allocate the right number 
for the class (two i32's for the f64 in this case).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57862 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-21 00:45:36 +00:00
Evan Cheng
09e8ca8a58 Add skeleton for the pre-register allocation live interval splitting pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57847 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-20 21:44:59 +00:00
Dan Gohman
d659d50482 Fast-isel no longer an experiment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57845 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-20 21:30:12 +00:00
Evan Cheng
11a26f3697 Add a register class -> virtual registers map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57844 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-20 20:03:28 +00:00
Duncan Sands
d398672ddd Support operations like fp_to_uint with a vector
result type when the result type is legal but
not the operand type.  Add additional support
for EXTRACT_SUBVECTOR and CONCAT_VECTORS,
needed to handle such cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57840 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-20 16:31:21 +00:00
Duncan Sands
b5f68e241f LegalizeTypes support for atomic operation promotion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57838 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-20 16:17:42 +00:00
Duncan Sands
49c18cce97 Use DAG.getIntPtrConstant rather than DAG.getConstant
with TLI.getPointerTy for a small simplification.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57837 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-20 16:14:43 +00:00
Duncan Sands
7e49822875 Always use either MVT::i1 or getSetCCResultType for
the condition of a SELECT node.  Make sure that the
correct extension type (any-, sign- or zero-extend)
is used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57836 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-20 16:13:04 +00:00
Duncan Sands
ef5b199905 Formatting - no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57834 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-20 16:06:47 +00:00
Duncan Sands
f6e29499ac Don't use a random type for the select condition,
use an MVT::i1 and simplify the code while there.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57833 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-20 16:04:57 +00:00
Bill Wendling
a1dc602542 Set N->OperandList to 0 after deletion. Otherwise, it's possible that it will
be either deleted or referenced afterwards.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57786 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-19 20:51:12 +00:00
Bill Wendling
181b627f62 Fix comment. Other formatting changes. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57785 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-19 20:34:04 +00:00
Duncan Sands
0e3da1def4 Vector shuffle mask elements may be "undef". Handle
this everywhere in LegalizeTypes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57783 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-19 15:00:25 +00:00
Duncan Sands
94989acaab Use a legal integer type for vector shuffle mask
elements.  Otherwise LegalizeTypes will, reasonably
enough, legalize the mask, which may result in it
no longer being a BUILD_VECTOR node (LegalizeDAG
simply ignores the legality or not of vector masks).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57782 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-19 14:58:05 +00:00
Chris Lattner
2a0b96c2c7 Reapply r57699 with a fix to not crash on asms with multiple results. Unlike
the previous patch this one actually passes make check.

"Fix PR2356 on PowerPC: if we have an input and output that are tied together
that have different sizes (e.g. i32 and i64) make sure to reserve registers for
the bigger operand."



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57771 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-18 18:49:30 +00:00
Dan Gohman
668aff6623 Don't truncate GlobalAddress offsets to int in debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57770 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-18 18:22:42 +00:00
Evan Cheng
4ed4329c37 By min, I mean max.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57766 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-18 05:21:37 +00:00
Evan Cheng
99fe34b9b2 When creating intervals, leave min(1, numdefs) holes after each instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57765 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-18 05:18:55 +00:00
Dan Gohman
6520e20e4f Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)

This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.

This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.

Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.

The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-18 02:06:02 +00:00
Dan Gohman
95915730de Revert r57699. It's causing regressions in
test/CodeGen/X86/2008-09-17-inline-asm-1.ll
and a few others, and it breaks the llvm-gcc build.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57747 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-18 01:03:45 +00:00
Dan Gohman
c227734855 Factor out the code for mapping LLVM IR condition opcodes to
ISD condition opcodes into helper functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57726 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17 21:16:08 +00:00
Evan Cheng
af42fe36ac Fix PR2898. Spiller delete a store for reuse before it knows for sure the reuse happened.
Patch by Lang Hames!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57720 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17 20:56:41 +00:00
Chris Lattner
cfc14c153a add support for 128 bit aggregates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57715 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17 19:59:51 +00:00
Bill Wendling
a9f0cc4ced The Dwarf writer was comparing mangled and unmangled names for C++ code when we
have an unreachable block in a function. This was triggering the assert. This is
a horrid hack to cover this up.

Oh! for a good debug info architecture!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57714 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17 18:48:57 +00:00
Mon P Wang
c4d1021ead Added MemIntrinsicNode which is useful to represent target intrinsics that
touches memory and need an associated MemOperand


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57712 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17 18:22:58 +00:00
Dan Gohman
8c1a6ca22a Factor out the code for mapping LLVM IR condition opcodes to
ISD condition opcodes into helper functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57710 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17 18:18:45 +00:00
Chris Lattner
0c52644cd8 Fix PR2356 on PowerPC: if we have an input and output that are tied together
that have different sizes (e.g. i32 and i64) make sure to reserve registers for
the bigger operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57699 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17 17:52:49 +00:00
Chris Lattner
81249c95ce refactor some code into a helper method, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57690 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17 17:05:25 +00:00
Chris Lattner
6bdcda3d3e Keep track of *which* input constraint matches an output
constraint.  Reject asms where an output has multiple
input constraints tied to it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57687 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17 16:47:46 +00:00
Chris Lattner
58f15c482a add an assert so that PR2356 explodes instead of running off an
array.  Improve some minor comments, refactor some helpers in
AsmOperandInfo.  No functionality change for valid code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57686 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17 16:21:11 +00:00
Evan Cheng
6784598895 Fix a very subtle spiller bug: UpdateKills should not forget to track defs of aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57673 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17 06:16:07 +00:00
Dan Gohman
74feef261a Define patterns for shld and shrd that match immediate
shift counts, and patterns that match dynamic shift counts
when the subtract is obscured by a truncate node.

Add DAGCombiner support for recognizing rotate patterns
when the shift counts are defined by truncate nodes.

Fix and simplify the code for commuting shld and shrd
instructions to work even when the given instruction doesn't
have a parent, and when the caller needs a new instruction.

These changes allow LLVM to use the shld, shrd, rol, and ror
instructions on x86 to replace equivalent code using two
shifts and an or in many more cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57662 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17 01:23:35 +00:00
Dan Gohman
131161bc6e Rename AliasSet to SubRegs, to reflect changes in the surrounding code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57618 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-16 01:06:18 +00:00
Dan Gohman
7ddcadc7ee Move the include of MachineLocation.h into MachineModuleInfo.h
because it declares a std::vector<MachineMove>, and strict
concept checking requires the definition of MachineMove to be
available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57617 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-16 00:20:14 +00:00
Dan Gohman
b382c4dc23 Fix a subtle bug in DeadMachineInstructionElim's liveness
computation. A def of a register doesn't necessarily kill
live super-registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57614 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-16 00:11:23 +00:00
Dan Gohman
26367472a2 Adjust whitespace in debug messages to be more consistent
with other debug messages.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57543 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-15 02:57:38 +00:00
Evan Cheng
7f04268176 - Add target lowering hooks that specify which setcc conditions are illegal,
i.e. conditions that cannot be checked with a single instruction. For example,
SETONE and SETUEQ on x86.
- Teach legalizer to implement *illegal* setcc as a and / or of a number of
legal setcc nodes. For now, only implement FP conditions. e.g. SETONE is
implemented as SETO & SETNE, SETUEQ is SETUO | SETEQ.
- Move x86 target over.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57542 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-15 02:05:31 +00:00