have an unreachable block in a function. This was triggering the assert. This is
a horrid hack to cover this up.
Oh! for a good debug info architecture!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57714 91177308-0d34-0410-b5e6-96231b3b80d8
in 32-bit mode instead of assigning a register pair. This has nothing to
do with PR2356, but I happened to notice it while working on it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57704 91177308-0d34-0410-b5e6-96231b3b80d8
array. Improve some minor comments, refactor some helpers in
AsmOperandInfo. No functionality change for valid code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57686 91177308-0d34-0410-b5e6-96231b3b80d8
distinguished from normal (untagged) ones
as per review comment.
I am sufficiently unaquainted with doxygen to
defer the markup to someone with more experience.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57676 91177308-0d34-0410-b5e6-96231b3b80d8
constants that don't fit in an int. This fixes
"this decimal constant is unsigned only in ISO C90"
warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57668 91177308-0d34-0410-b5e6-96231b3b80d8
use a SUB instruction instead of an ADD, because -128 can be
encoded in an 8-bit signed immediate field, while +128 can't be.
This avoids the need for a 32-bit immediate field in this case.
A similar optimization applies to 64-bit adds with 0x80000000,
with the 32-bit signed immediate field.
To support this, teach tablegen how to handle 64-bit constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57663 91177308-0d34-0410-b5e6-96231b3b80d8
shift counts, and patterns that match dynamic shift counts
when the subtract is obscured by a truncate node.
Add DAGCombiner support for recognizing rotate patterns
when the shift counts are defined by truncate nodes.
Fix and simplify the code for commuting shld and shrd
instructions to work even when the given instruction doesn't
have a parent, and when the caller needs a new instruction.
These changes allow LLVM to use the shld, shrd, rol, and ror
instructions on x86 to replace equivalent code using two
shifts and an or in many more cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57662 91177308-0d34-0410-b5e6-96231b3b80d8
using the 'volatile' qualifier. This should not have any operational consequences
on code, because tags should always be stripped off (giving a non-volatile pointer)
before dereferencing. The new qualification is there to catch some attempts to use
tagged pointers in a context where an untagged pointer is appropriate.
Notably this approach does not catch dereferencing of tagged pointers, but helps
in separating the two concepts a bit.
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x86 backend. These will all be answered with "patches welcome", so
a PR doesn't help drive them along.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57630 91177308-0d34-0410-b5e6-96231b3b80d8
basically working, feel free to remove the tag. The other targets have
really basic things that break them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57628 91177308-0d34-0410-b5e6-96231b3b80d8
because it declares a std::vector<MachineMove>, and strict
concept checking requires the definition of MachineMove to be
available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57617 91177308-0d34-0410-b5e6-96231b3b80d8
copies of a value, and add several additional utilities to make
SmallVector better conform to the Container concept.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57616 91177308-0d34-0410-b5e6-96231b3b80d8
