Commit Graph

82396 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
fcad79671f Compute secondary sub-registers.
The sub-registers explicitly listed in SubRegs in the .td files form a
tree. In a complicated register bank, it is possible to have
sub-register relationships across sub-trees. For example, the ARM NEON
double vector Q0_Q1 is a tree:

  Q0_Q1 = [Q0, Q1],  Q0 = [D0, D1], Q1 = [D2, D3]

But we also define the DPair register D1_D2 = [D1, D2] which is fully
contained in Q0_Q1.

This patch teaches TableGen to find such sub-register relationships, and
assign sub-register indices to them. In the example, TableGen will
create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a
sub-register of Q0_Q1.

This will eventually enable the coalescer to handle copies of skewed
sub-registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156587 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 23:27:10 +00:00
Nuno Lopes
9d236f909c objectsize: add support for GEPs with non-constant indexes
add an additional parameter to InstCombiner::EmitGEPOffset() to force it to *not* emit operations with NUW flag

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156585 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 23:17:35 +00:00
Preston Gurd
deaa3f3e52 Added X86 Atom latencies for instructions in X86InstrInfo.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156579 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 21:58:35 +00:00
Eric Christopher
05b7a50210 Add support for the 'X' inline asm operand modifier.
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156577 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 21:48:22 +00:00
Andrew Trick
89c324bf11 misched: Print machineinstrs with -debug-only=misched
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156576 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 21:06:21 +00:00
Andrew Trick
28ebc89c41 misched: tracing register pressure heuristics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156575 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 21:06:19 +00:00
Andrew Trick
7196a8ff21 misched: Add register pressure backoff to ConvergingScheduler.
Prioritize the instruction that comes closest to keeping pressure
under the target's limit. Then prioritize instructions that avoid
increasing the max pressure in the scheduled region. The max pressure
heuristic is a tad aggressive. Later I'll fix it to consider the
unscheduled pressure as well.

WIP: This is mostly functional but untested and not likely to do much good yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156574 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 21:06:16 +00:00
Andrew Trick
16716c7302 misched: Release only unscheduled nodes into ReadyQ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156573 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 21:06:14 +00:00
Andrew Trick
d38f87eeec misched: Added ReadyQ container wrapper for Top and Bottom Queues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156572 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 21:06:12 +00:00
Andrew Trick
7f8ab785af misched: Introducing Top and Bottom register pressure trackers during scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156571 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 21:06:10 +00:00
Sirish Pande
0cfb5cfe97 Hexagon V5 Support - V5 td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156569 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 20:24:28 +00:00
Sirish Pande
7517bbc91a Hexagon V5 FP Support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156568 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 20:20:25 +00:00
Andrew Trick
55ba5dff3c RegPressure: API for speculatively checking instruction pressure.
Added getMaxExcessUpward/DownwardPressure. They somewhat abuse the
tracker by speculatively handling an instruction out of order. But it
is convenient for now. In the future, we will cache each instruction's
pressure contribution to make this efficient.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156561 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 19:11:52 +00:00
Andrew Trick
d253035339 RegPressure: fix array index iteration style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156560 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 19:11:49 +00:00
Dan Gohman
b401e3bd16 Teach DeadStoreElimination to eliminate exit-block stores with phi addresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156558 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 18:57:38 +00:00
Manman Ren
fe65d98dad Revert: 156550 "ARM: peephole optimization to remove cmp instruction"
This commit broke an external linux bot and gave a compile-time warning.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 18:49:43 +00:00
Jakob Stoklund Olesen
148f392195 Precompute lists of explicit sub-registers and indices.
The .td files specify a tree of sub-registers. Store that tree as
ExplicitSubRegs lists in CodeGenRegister instead of extracting it from
the Record when needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156555 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 17:46:18 +00:00
Dan Gohman
ac84461e5a Rewrite ScalarEvolution::hasOperand to use an explicit worklist instead
of recursion, to avoid excessive stack usage on deep expressions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156554 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 17:21:30 +00:00
Nuno Lopes
e54874471c teach DSE and isInstructionTriviallyDead() about calloc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156553 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 17:14:00 +00:00
Joel Jones
9777f61bfe formatting change: strip debug info from test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156551 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 16:55:31 +00:00
Manman Ren
8ae4f062e4 ARM: peephole optimization to remove cmp instruction
This patch will optimize the following cases:
  sub r1, r3 | sub r1, imm
  cmp r3, r1 or cmp r1, r3 | cmp r1, imm
  bge L1

TO
  subs r1, r3
  bge  L1 or ble L1

If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.

rdar: 10734411


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156550 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 16:48:21 +00:00
Joel Jones
9df72a93ef Fix a problem with incomplete equality testing of PHINodes in
Instruction::IsIdenticalToWhenDefined.

This manifested itself when inlining two calls to the same function.  The 
inlined function had a switch statement that returned one of a set of 
global variables.  Without this modification, the two phi instructions that 
chose values from the branches of the switch instruction inlined from the 
callee were considered equivalent and jump-threading replaced a load for the 
first switch value with a phi selecting from the second switch, thereby 
producing incorrect code.

This patch has been tested with "make check-all", "lnt runteste nt", and 
llvm self-hosted, and on the original program that had this problem, 
wireshark.

<rdar://problem/11025519>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156548 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 15:59:41 +00:00
Nadav Rotem
b88e8dd31d Fix merge-typo and cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156541 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 12:50:02 +00:00
Nadav Rotem
b210651654 AVX2: Add an additional broadcast idiom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156540 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 12:39:13 +00:00
Nadav Rotem
5fc2187a02 Generate AVX/AVX2 shuffles even when there is a memory op somewhere else in the program.
Starting r155461 we are able to select patterns for vbroadcast even when the load op is used by other users.

Fix PR11900.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156539 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 12:22:05 +00:00
Andrew Trick
7b521ad6ee Fix TableGen's RegPressureSet weight normalization to handle subreg DAGS.
I initially assumed that the subreg graph was a tree. That may not be true.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156524 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 00:32:15 +00:00
Jim Grosbach
77966fab9e ExecutionEngine: Check for NULL ErrorStr before using it.
Patch by Yury Mikhaylov <yury.mikhaylov@gmail.com>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156523 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 00:31:50 +00:00
Jakob Stoklund Olesen
08dc5f2adb Fix warning text.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156521 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 23:43:30 +00:00
Dan Gohman
95b8cf1f11 Fix the objc_storeStrong recognizer to stop before walking off the
end of a basic block if there's no store.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156520 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 23:08:33 +00:00
Jakob Stoklund Olesen
ca313e1efa Compute a backwards SubReg -> SubRegIndex map for each register.
This mapping is for internal use by TableGen. It will not be exposed in
the generated files.

Unfortunately, the mapping is not completely well-defined. The X86 xmm
registers appear with multiple sub-register indices in the ymm
registers. This is because of the odd idempotent sub_sd and sub_ss
sub-register indices. I hope to be able to eliminate them entirely, so
we can require the sub-registers to form a tree.

For now, just place the canonical sub_xmm index in the mapping, and
ignore the idempotents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156519 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 22:15:00 +00:00
Jakob Stoklund Olesen
da2be82434 Rename getSubRegs() to computeSubRegs().
That's what it does.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156518 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 22:09:17 +00:00
Nuno Lopes
e3305b1750 objectsize:
refactor code a bit to enable future changes to support run-time information
add support to compute allocation sizes at run-time if penalty > 1 (e.g., malloc(x), calloc(x, y), and VLAs)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156515 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 21:30:57 +00:00
Chad Rosier
9166d23327 Add unittests for Triple::getMacOSXVersion and Triple::getiOSVersion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156507 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 19:31:41 +00:00
Danil Malyshev
fd39afb5e1 Added a regress test for the bug #9964 before close it.
This bug was fixed by Jim Grosbach in #138879, thanks Jim!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156505 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 19:07:04 +00:00
Roman Divacky
d9b41b339d Mark .opd @progbits, thus avoiding a warning from asm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156494 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 18:24:23 +00:00
Chad Rosier
537c2f5b2a Set the default iOS version to 3.0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156492 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 18:23:00 +00:00
Bob Wilson
0d38d3a000 Use the cpuid 64 bit flag to pick the default CPU name for an unknown model.
For the Family 6 switch in sys::getHostCPUName, an unrecognized model was
reported as "i686".  That's a really bad default since it means that new
CPUs will be treated as if they can only use 32-bit code.  This just looks
at the cpuid extended feature flag for 64 bit support, and if that is set,
it uses a default x86-64 cpu.  Similar logic is already used for the Family
15 code.  <rdar://problem/11314502>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156486 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 17:47:03 +00:00
Chad Rosier
26bbdeed6c Don't return true on a function with a void return type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156484 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 17:38:47 +00:00
Chad Rosier
ecee47eab4 Add Triple::getiOSVersion.
This new function provides a way to get the iOS version number from ios triples.
Part of rdar://11409204


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156483 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 17:23:48 +00:00
Hans Wennborg
5c87b4958d Introduce llvm-c function LLVMPrintModuleToFile.
This lets you save the textual representation of the LLVM IR to a file.
Before this patch it could only be printed to STDERR from llvm-c.

Patch by Carlo Kok!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156479 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 16:54:17 +00:00
Nuno Lopes
30759542aa change the objectsize intrinsic signature: add a 3rd parameter to denote the maximum runtime performance penalty that the user is willing to accept.
This commit only adds the parameter. Code taking advantage of it will follow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156473 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 15:52:43 +00:00
Manuel Klimek
80fa4723b9 Make it possible to switch off solution folders. VS Express does not support
them, and requires the user to click away one error message per folder on
project load.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156472 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 15:10:54 +00:00
Filipe Cabecinhas
7305295538 Fixed a typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156471 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 14:43:50 +00:00
Bill Wendling
f24fde20c8 Supply a C interface to the "LinkModules" method.
Patch by Andrew Wilkins!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156469 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 08:55:40 +00:00
Craig Topper
b12af898c3 Remove unused variable to get rid of warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156466 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 07:08:58 +00:00
Akira Hatanaka
2b409b65d4 Add another peephole pattern for conditional moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 02:29:29 +00:00
Jakob Stoklund Olesen
cf661a040c Use ptr_rc_tailcall instead of GR32_TC.
The getPointerRegClass() hook will return GR32_TC, or whatever is
appropriate for the current function.

Patch by Yiannis Tsiouris!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156459 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 01:50:09 +00:00
Akira Hatanaka
56ec9f2c09 Make register FP allocatable if the compiled function does not have dynamic
allocas.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156458 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 01:38:13 +00:00
Akira Hatanaka
a284acb8a7 Expand 64-bit shifts if target ABI is O32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156457 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 00:55:21 +00:00
Richard Trieu
220ee59b90 Remove unused variable to silence compiler warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156456 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 00:30:21 +00:00