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0104d9de04
- For now, loads of [r, r] addressing mode is the same as the [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should identify the former case and reduce the output latency by 1. - Also identify [r, r << 2] case. This special form of shifter addressing mode is "free". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117519 91177308-0d34-0410-b5e6-96231b3b80d8
28 lines
729 B
LLVM
28 lines
729 B
LLVM
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
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; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
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define float @test(float %a, float %b) {
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entry:
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%dum = fadd float %a, %b
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%0 = tail call float @fabsf(float %dum)
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%dum1 = fadd float %0, %b
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ret float %dum1
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}
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declare float @fabsf(float)
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; VFP2: test:
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; VFP2: vabs.f32 s1, s1
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; NFP1: test:
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; NFP1: vabs.f32 d1, d1
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; NFP0: test:
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; NFP0: vabs.f32 s1, s1
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; CORTEXA8: test:
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; CORTEXA8: vabs.f32 d1, d1
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; CORTEXA9: test:
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; CORTEXA9: vabs.f32 s1, s1
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