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0781c1f700
llvm-6502/test/MC/Disassembler/ARM
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Owen Anderson 0781c1f700 Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 21:26:40 +00:00
..
arm-tests.txt Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 2011-09-07 19:42:28 +00:00
basic-arm-instructions.txt Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered. 2011-08-26 23:32:08 +00:00
dg.exp
fp-encoding.txt Add some more comprehensive VFP decoding tests. 2011-08-15 21:29:01 +00:00
invalid-Bcc-thumb.txt Tighten Thumb1 branch predicate decoding. 2011-08-09 21:07:45 +00:00
invalid-BFI-arm.txt Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI. 2011-08-09 22:48:45 +00:00
invalid-CPS2p-arm.txt Tighten operand checking on CPS instructions. 2011-08-09 23:05:39 +00:00
invalid-CPS3p-arm.txt Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions. 2011-08-18 22:11:02 +00:00
invalid-DMB-thumb.txt Tighten operand checking on memory barrier instructions. 2011-08-09 23:25:42 +00:00
invalid-DSB-arm.txt Tighten operand checking on memory barrier instructions. 2011-08-09 23:25:42 +00:00
invalid-IT-CBNZ-thumb.txt Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block. 2011-09-08 22:42:49 +00:00
invalid-IT-thumb.txt Add a testcase for r138625. 2011-08-26 06:45:08 +00:00
invalid-LDC-form-arm.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-LDM-thumb.txt LDM writeback is not allowed if Rn is in the target register list. 2011-09-09 23:13:33 +00:00
invalid-LDR_POST-arm.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-LDR_PRE-arm.txt invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. 2011-08-26 20:43:14 +00:00
invalid-LDRB_POST-arm.txt Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. 2011-08-17 17:44:15 +00:00
invalid-LDRD_PRE-thumb.txt Thumb2 assembly parsing and encoding for LDRD(immediate). 2011-09-08 22:07:06 +00:00
invalid-LDRD-arm.txt Test commit; adding test for invalid LDRD which was part of the patch for r137647 but seemingly didn't get svn add'ed. 2011-08-18 18:03:02 +00:00
invalid-LDRrs-arm.txt Fix single word and unsigned byte data transfer instruction encodings so that 2011-03-31 19:28:35 +00:00
invalid-LDRT-arm.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-LSL-regform.txt Tighten operand checking of register-shifted-register operands. 2011-08-09 23:33:27 +00:00
invalid-MCR-arm.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-MOVr-arm.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-MOVs-arm.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-MOVs-LSL-arm.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-MOVTi16-arm.txt Push GPRnopc through a large number of instruction definitions to tighten operand decoding. 2011-08-10 00:03:03 +00:00
invalid-MSRi-arm.txt Continue to tighten decoding by performing more operand validation. 2011-08-11 20:21:46 +00:00
invalid-RFEorLDMIA-arm.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-RSC-arm.txt Tighten operand checking of register-shifted-register operands. 2011-08-09 23:33:27 +00:00
invalid-SBFX-arm.txt Push GPRnopc through a large number of instruction definitions to tighten operand decoding. 2011-08-10 00:03:03 +00:00
invalid-SMLAD-arm.txt Push GPRnopc through a large number of instruction definitions to tighten operand decoding. 2011-08-10 00:03:03 +00:00
invalid-SRS-arm.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-SSAT-arm.txt Push GPRnopc through a large number of instruction definitions to tighten operand decoding. 2011-08-10 00:03:03 +00:00
invalid-STMIA_UPD-thumb.txt Continue to tighten decoding by performing more operand validation. 2011-08-11 20:21:46 +00:00
invalid-STRBrs-arm.txt Continue to tighten decoding by performing more operand validation. 2011-08-11 20:21:46 +00:00
invalid-SXTB-arm.txt Push GPRnopc through a large number of instruction definitions to tighten operand decoding. 2011-08-10 00:03:03 +00:00
invalid-t2Bcc-thumb.txt Tighten operand checking on memory barrier instructions. 2011-08-09 23:25:42 +00:00
invalid-t2LDRBT-thumb.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-t2LDREXD-thumb.txt Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 2011-09-07 19:42:28 +00:00
invalid-t2LDRSHi8-thumb.txt Improve operand validation for Thumb2 addressing modes. 2011-08-11 20:40:40 +00:00
invalid-t2LDRSHi12-thumb.txt Improve operand validation for Thumb2 addressing modes. 2011-08-11 20:40:40 +00:00
invalid-t2PUSH-thumb.txt Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either. 2011-09-12 21:28:46 +00:00
invalid-t2STR_POST-thumb.txt Improve operand validation for Thumb2 addressing modes. 2011-08-11 20:40:40 +00:00
invalid-t2STRD_PRE-thumb.txt Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 2011-09-07 19:42:28 +00:00
invalid-t2STREXB-thumb.txt Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 2011-09-07 19:42:28 +00:00
invalid-t2STREXD-thumb.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-UMAAL-arm.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-UQADD8-arm.txt Push GPRnopc through a large number of instruction definitions to tighten operand decoding. 2011-08-10 00:03:03 +00:00
invalid-VLD1DUPq8_UPD-arm.txt Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 2011-09-07 19:42:28 +00:00
invalid-VLD3DUPd32_UPD-thumb.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-VLDMSDB_UPD-arm.txt Improve error checking in the new ARM disassembler. Patch by James Molloy. 2011-08-11 18:24:51 +00:00
invalid-VQADD-arm.txt Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 2011-09-07 19:42:28 +00:00
invalid-VST2b32_UPD-arm.txt Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 2011-09-07 19:42:28 +00:00
memory-arm-instructions.txt Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact. 2011-08-15 20:51:32 +00:00
neon-tests.txt Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 2011-09-07 19:42:28 +00:00
neon.txt Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 2011-09-07 19:42:28 +00:00
neont2.txt Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 2011-09-07 19:42:28 +00:00
thumb1.txt Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. 2011-08-26 18:09:22 +00:00
thumb2.txt Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions. 2011-09-23 21:26:40 +00:00
thumb-printf.txt Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 2011-09-07 19:42:28 +00:00
thumb-tests.txt Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123. 2011-09-21 23:44:46 +00:00