Hal Finkel 089a5f8a8c DAGCombiner: Constant folding around pre-increment loads/stores ... Previously, even when a pre-increment load or store was generated, we often needed to keep a copy of the original base register for use with other offsets. If all of these offsets are constants (including the offset which was combined into the addressing mode), then this is clearly unnecessary. This change adjusts these other offsets to use the new incremented address. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174746 91177308-0d34-0410-b5e6-96231b3b80d8		2013-02-08 21:35:47 +00:00
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AArch64	Implement external weak (ELF) symbols on AArch64	2013-02-06 16:43:33 +00:00
ARM	Revert 172027 and 174336. Remove diagnostics about over-aligned stack objects.	2013-02-08 20:35:15 +00:00
CPP
Generic	For inline asm:	2013-01-11 18:12:39 +00:00
Hexagon	Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle	2013-02-05 19:20:45 +00:00
MBlaze
Mips	When Mips16 frames grow large, the immediate field may exceed the maximum	2013-02-08 03:57:41 +00:00
MSP430
NVPTX
PowerPC	DAGCombiner: Constant folding around pre-increment loads/stores	2013-02-08 21:35:47 +00:00
R600	R600: Add support for SET*_DX10 instructions	2013-02-07 14:02:35 +00:00
SI	Add R600 backend	2012-12-11 21:25:42 +00:00
SPARC
Thumb
Thumb2	FileCheck-ify some grep tests	2013-01-25 22:11:46 +00:00
X86	This is a follow-up on r174446, now taking Atom processors into	2013-02-06 20:43:57 +00:00
XCore