Kalle Raiskila 0cc5b1f60e Division by pow-of-2 is not cheap on SPU, do it with ...

shifts.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120022 91177308-0d34-0410-b5e6-96231b3b80d8

2010-11-23 13:27:59 +00:00

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useful-harnesses

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2009-01-01-BrCond.ll

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2010-04-07-DbgValueOtherTargets.ll

Split big test into multiple directories to cater to

2010-04-07 20:43:35 +00:00

and_ops.ll

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arg_ret.ll

Fix memory access lowering on SPU, adding

2010-11-12 10:14:03 +00:00

bigstack.ll

Have SPU handle halfvec stores aligned by 8 bytes.

2010-08-09 16:33:00 +00:00

bss.ll

Make sure this test tests something.

2010-04-09 19:03:31 +00:00

call_indirect.ll

Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway.

2010-07-16 04:45:42 +00:00

call.ll

Fix SPU BE to use all the available return registers.

2010-08-24 11:50:48 +00:00

crash.ll

teach cellspu how to return i8 and i16 from calls,

2010-04-20 05:36:09 +00:00

ctpop.ll

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dg.exp

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div_ops.ll

Division by pow-of-2 is not cheap on SPU, do it with

2010-11-23 13:27:59 +00:00

dp_farith.ll

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eqv.ll

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extract_elt.ll

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fcmp32.ll

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fcmp64.ll

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fdiv.ll

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fneg-fabs.ll

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i8ops.ll

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i64ops.ll

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icmp8.ll

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icmp16.ll

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icmp32.ll

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icmp64.ll

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immed16.ll

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immed32.ll

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immed64.ll

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int2fp.ll

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intrinsics_branch.ll

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intrinsics_float.ll

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intrinsics_logical.ll

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jumptable.ll

Mark the SPU 'lr' instruction to never have side effects.

2010-06-21 15:08:16 +00:00

loads.ll

Fix memory access lowering on SPU, adding

2010-11-12 10:14:03 +00:00

mul_ops.ll

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mul-with-overflow.ll

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nand.ll

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or_ops.ll

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private.ll

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rotate_ops.ll

Fix a bug with extractelement on SPU.

2010-11-22 16:28:26 +00:00

select_bits.ll

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sext128.ll

Improve lowering of sext to i128 on SPU.

2010-10-18 09:34:19 +00:00

shift_ops.ll

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shuffles.ll

Fix CellSPU vector shuffles, again.

2010-09-08 11:53:38 +00:00

sp_farith.ll

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stores.ll

Fix memory access lowering on SPU, adding

2010-11-12 10:14:03 +00:00

storestruct.ll

"on the rare occasion the SPU BE produces illegal assembly - it tries to emit an add instruction of the form 'a reg, reg, imm'."

2010-05-04 17:58:46 +00:00

struct_1.ll

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sub_ops.ll

Fix encoding of 'sf' and 'sfh' instructions.

2010-05-10 08:13:49 +00:00

trunc.ll

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v2f32.ll

Change v64 datalayout in SPU.

2010-10-26 10:45:47 +00:00

v2i32.ll

Change v64 datalayout in SPU.

2010-10-26 10:45:47 +00:00

vec_const.ll

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vecinsert.ll

Fix SPU to cope with vector insertelement to an undef position.

2010-06-09 09:58:17 +00:00