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argaddr.ll
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add a "load effective address"
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2006-08-17 17:09:40 +00:00 |
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bits.ll
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implement shl and sra
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2006-09-08 17:36:23 +00:00 |
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branch.ll
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add the SETULT condition code
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2006-09-03 13:19:16 +00:00 |
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call.ll
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add blx
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2006-10-18 16:21:43 +00:00 |
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constants.ll
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print common symbols
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2006-10-19 13:30:40 +00:00 |
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dg.exp
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create test/Regression/CodeGen/ARM/ and add a minimal test to it
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2006-05-25 10:49:19 +00:00 |
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div.ll
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expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM
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2006-10-17 21:05:33 +00:00 |
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fp.ll
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cleanup some tests
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2006-10-17 20:20:07 +00:00 |
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fparith.ll
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add FABSS and FABSD
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2006-10-17 20:33:13 +00:00 |
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fpcmp.ll
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cleanup some tests
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2006-10-17 20:20:07 +00:00 |
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fpconv.ll
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cleanup some tests
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2006-10-17 20:20:07 +00:00 |
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fpmem.ll
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remove extra [] in stores
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2006-10-17 18:29:14 +00:00 |
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hello.ll
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use a 'register pressure reducing' scheduler
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2006-08-04 12:48:42 +00:00 |
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ldr.ll
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select code like
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2006-08-14 19:01:24 +00:00 |
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load.ll
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implement LDRB, LDRSB, LDRH and LDRSH
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2006-10-16 17:17:22 +00:00 |
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long.ll
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add the immediate to the Offset in eliminateFrameIndex
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2006-10-17 14:34:02 +00:00 |
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longarith.ll
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expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS
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2006-10-16 21:10:32 +00:00 |
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mem.ll
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implement STRB and STRH
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2006-10-23 20:34:27 +00:00 |
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mul.ll
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Implement a MachineFunctionPass to fix the mul instruction
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2006-09-19 15:49:25 +00:00 |
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ret_arg1.ll
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added some tests for argument passing
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2006-06-01 22:01:25 +00:00 |
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ret_arg2.ll
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added some tests for argument passing
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2006-06-01 22:01:25 +00:00 |
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ret_arg3.ll
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added some tests for argument passing
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2006-06-01 22:01:25 +00:00 |
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ret_arg4.ll
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added some tests for argument passing
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2006-06-01 22:01:25 +00:00 |
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ret_arg5.ll
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initial implementation of ARMRegisterInfo::eliminateFrameIndex
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2006-06-18 00:08:07 +00:00 |
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ret_void.ll
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added some tests for argument passing
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2006-06-01 22:01:25 +00:00 |
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select.ll
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more condition codes
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2006-09-21 13:06:26 +00:00 |
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vargs2.ll
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expand ISD::VACOPY
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2006-10-24 20:15:21 +00:00 |
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vargs.ll
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fix the spill code
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2006-08-09 16:41:12 +00:00 |
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