Richard Sandiford 16277c4698 [SystemZ] Add NC, OC and XC ... For now these are just used to handle scalar ANDs, ORs and XORs in which all operands are memory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190041 91177308-0d34-0410-b5e6-96231b3b80d8		2013-09-05 10:36:45 +00:00
..
AArch64	Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:	2013-09-04 09:28:24 +00:00
ARM	Expand and rewrite comment.	2013-09-04 21:23:23 +00:00
CPP
Generic
Hexagon	Debug Info: add an identifier field to DICompositeType.	2013-08-26 22:39:55 +00:00
Inputs	Debug Info: add an identifier field to DICompositeType.	2013-08-26 22:39:55 +00:00
Mips	Make sure we don't generate stubs for any of these functions because they	2013-09-01 04:12:59 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Call support for fast-isel.	2013-08-30 22:18:55 +00:00
R600	R600: Use shared op optimization when checking cycle compatibility	2013-09-04 19:53:54 +00:00
SPARC	[Sparc] Correctly handle call to functions with ReturnsTwice attribute.	2013-09-05 05:32:16 +00:00
SystemZ	[SystemZ] Add NC, OC and XC	2013-09-05 10:36:45 +00:00
Thumb	ARM: Use "dmb sy" for barriers on M-class CPUs	2013-08-28 14:39:19 +00:00
Thumb2
X86	mi-sched: Force bottom up scheduling for generic targets.	2013-09-04 23:54:00 +00:00
XCore