llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-19 17:37:24 +00:00

History

Evan Cheng da47e6e0d0 Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8		2008-03-15 00:03:38 +00:00
..
IA64.h
IA64.td
IA64AsmPrinter.cpp	Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries.	2008-02-28 00:43:03 +00:00
IA64Bundling.cpp
IA64InstrBuilder.h
IA64InstrFormats.td
IA64InstrInfo.cpp
IA64InstrInfo.h	Rename MRegisterInfo to TargetRegisterInfo.	2008-02-10 18:45:23 +00:00
IA64InstrInfo.td	Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.	2008-03-15 00:03:38 +00:00
IA64ISelDAGToDAG.cpp	Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead.	2008-02-04 23:06:48 +00:00
IA64ISelLowering.cpp	Default ISD::PREFETCH to expand.	2008-03-10 19:38:10 +00:00
IA64ISelLowering.h	- Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency.	2008-03-10 23:49:09 +00:00
IA64MachineFunctionInfo.h
IA64RegisterInfo.cpp	Rename MRegisterInfo to TargetRegisterInfo.	2008-02-10 18:45:23 +00:00
IA64RegisterInfo.h	Remove bunch of gcc 4.3-related warnings from Target	2008-02-20 11:22:39 +00:00
IA64RegisterInfo.td	make sure ar.pfs is in a register class, this fixes test/CodeGen/IA64/ret-0.ll	2008-03-09 20:12:44 +00:00
IA64TargetAsmInfo.cpp
IA64TargetAsmInfo.h
IA64TargetMachine.cpp	Use PassManagerBase instead of FunctionPassManager for functions	2008-03-11 22:29:46 +00:00
IA64TargetMachine.h	Use PassManagerBase instead of FunctionPassManager for functions	2008-03-11 22:29:46 +00:00
Makefile
README	Stuff noticed while grepping code	2008-02-11 23:47:56 +00:00

README

TODO:
  - Un-bitrot ISel
  - Hook up If-Conversion a la ARM target
  - Hook up all branch analysis functions
  - Instruction scheduling
  - Bundling
  - Dynamic Optimization
  - Testing and bugfixing
  - stop passing FP args in both FP *and* integer regs when not required
  - allocate low (nonstacked) registers more aggressively
  - clean up and thoroughly test the isel patterns.
  - fix stacked register allocation order: (for readability) we don't want
    the out? registers being the first ones used
  - fix up floating point
    (nb http://gcc.gnu.org/wiki?pagename=ia64%20floating%20point )
  - bundling!
    (we will avoid the mess that is:
     http://gcc.gnu.org/ml/gcc/2003-12/msg00832.html )
  - instruction scheduling (hmmmm! ;)
  - counted loop support
  - make integer + FP mul/div more clever (we have fixed pseudocode atm)
  - track and use comparison complements

INFO:
  - we are strictly LP64 here, no support for ILP32 on HP-UX. Linux users
    don't need to worry about this.
  - i have instruction scheduling/bundling pseudocode, that really works
    (has been tested, albeit at the perl-script level).
    so, before you go write your own, send me an email!

KNOWN DEFECTS AT THE CURRENT TIME:
  - C++ vtables contain naked function pointers, not function descriptors,
  which is bad. see http://llvm.cs.uiuc.edu/bugs/show_bug.cgi?id=406
  - varargs are broken
  - alloca doesn't work (indeed, stack frame layout is bogus)
  - no support for big-endian environments
  - (not really the backend, but...) the CFE has some issues on IA64.
    these will probably be fixed soon.
  
ACKNOWLEDGEMENTS:
  - Chris Lattner (x100)
  - Other LLVM developers ("hey, that looks familiar")

CONTACT:
  - You can email me at duraid@octopus.com.au. If you find a small bug,
    just email me. If you find a big bug, please file a bug report
    in bugzilla! http://llvm.cs.uiuc.edu is your one stop shop for all
    things LLVM.