llvm-6502/test/CodeGen
Jakob Stoklund Olesen 20bc5acfb6 Don't depend on the physreg coalescing order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130818 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04 01:01:47 +00:00
..
Alpha If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0. 2010-12-06 22:39:26 +00:00
ARM Fix a bunch of ARM tests to be register allocation independent. 2011-05-03 22:31:21 +00:00
Blackfin Don't completely eliminate identity copies that also modify super register liveness. 2011-03-31 17:55:25 +00:00
CBackend
CellSPU don't test for codegen of 'store undef' 2011-04-09 02:31:26 +00:00
CPP
Generic Un-XFAIL this test for ARM. <rdar://problem/7662569> 2011-04-20 21:47:45 +00:00
MBlaze Add scheduling information for the MBlaze backend. 2011-04-11 22:31:52 +00:00
Mips Don't run this test through -regalloc=basic. 2011-05-04 01:01:44 +00:00
MSP430 Fix register-dependent test in MSP430. 2011-05-04 01:01:39 +00:00
PowerPC Add 130690 back. 2011-05-02 15:58:16 +00:00
PTX PTX: support for bitwise operations on predicates 2011-04-28 00:19:51 +00:00
SPARC These tests no longer require linear scan because reserved register coalescing is now universal. 2011-04-05 21:40:41 +00:00
SystemZ Fix SystemZ tests 2011-03-31 23:02:12 +00:00
Thumb Be careful about scheduling nodes above previous calls. It increase usages of 2011-04-26 21:31:35 +00:00
Thumb2 Weekly fix of register allocation dependent unit tests. 2011-04-30 01:37:52 +00:00
X86 Don't depend on the physreg coalescing order. 2011-05-04 01:01:47 +00:00
XCore Fix register-dependent XCore tests 2011-05-04 01:01:41 +00:00