Craig Topper 2dcd718c13 Update CanXFormVExtractWithShuffleIntoLoad to ensure bitcasts of loads only have one use. Matches DAGCombiner and prevents vector_shuffles from reaching isel. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150360 91177308-0d34-0410-b5e6-96231b3b80d8		2012-02-13 04:30:38 +00:00
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ARM	RegAlloc superpass: includes phi elimination, coalescing, and scheduling.	2012-02-10 04:10:36 +00:00
CBackend
CellSPU	This patch addresses the problem of poor code generation for the zext	2012-02-12 15:05:31 +00:00
CPP	Testcase for commit 149833 (use of an uninitialized variable noticed	2012-02-05 19:27:57 +00:00
Generic	Move test/CodeGen/Generic/2012-02-01-CoalescerBug.ll to CodeGen/ARM, for now. It requires TARGETS=arm.	2012-02-02 11:44:58 +00:00
Hexagon	VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA).	2012-02-01 22:13:57 +00:00
MBlaze
Mips	Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is	2012-02-03 04:33:00 +00:00
MSP430
PowerPC
PTX
SPARC
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X86	Update CanXFormVExtractWithShuffleIntoLoad to ensure bitcasts of loads only have one use. Matches DAGCombiner and prevents vector_shuffles from reaching isel.	2012-02-13 04:30:38 +00:00
XCore