llvm-6502/lib/Target/Sparc
Anton Korobeynikov f191c80cd7 Use TableGen to emit information for dwarf register numbers.
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-11 19:50:10 +00:00
..
DelaySlotFiller.cpp Drop 'const' 2007-05-03 01:11:54 +00:00
FPMover.cpp Drop 'const' 2007-05-03 01:11:54 +00:00
Makefile don't dist internal readme 2006-10-28 00:51:15 +00:00
README.txt Done 2006-02-09 20:00:19 +00:00
Sparc.h silence warnings 2006-11-03 01:11:05 +00:00
Sparc.td getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. 2006-05-18 00:12:58 +00:00
SparcAsmPrinter.cpp Eliminate the remaining uses of getTypeSize. This 2007-11-05 00:04:43 +00:00
SparcInstrFormats.td Change instruction description to split OperandList into OutOperandList and 2007-07-19 01:14:50 +00:00
SparcInstrInfo.cpp Add lengthof and endof templates that hide a lot of sizeof computations. 2007-09-07 04:06:50 +00:00
SparcInstrInfo.h RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. 2007-05-18 00:18:17 +00:00
SparcInstrInfo.td Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 2007-09-11 19:55:27 +00:00
SparcISelDAGToDAG.cpp Set ISD::FPOW to Expand. 2007-10-11 23:21:31 +00:00
SparcRegisterInfo.cpp Use TableGen to emit information for dwarf register numbers. 2007-11-11 19:50:10 +00:00
SparcRegisterInfo.h Use TableGen to emit information for dwarf register numbers. 2007-11-11 19:50:10 +00:00
SparcRegisterInfo.td Use TableGen to emit information for dwarf register numbers. 2007-11-11 19:50:10 +00:00
SparcSubtarget.cpp Patches to make the LLVM sources more -pedantic clean. Patch provided 2006-05-24 17:04:05 +00:00
SparcSubtarget.h Rename SPARC V8 target to be the LLVM SPARC target. 2006-02-05 05:50:24 +00:00
SparcTargetAsmInfo.cpp Break out target asm info into separate files. 2006-09-07 22:05:02 +00:00
SparcTargetAsmInfo.h More explicit keywords. 2007-09-25 20:27:06 +00:00
SparcTargetMachine.cpp long double patch 2 of N. Handle it in TargetData. 2007-08-03 20:20:50 +00:00
SparcTargetMachine.h 1. Remove condition on delete. 2006-09-07 23:39:26 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots