Nadav Rotem 2ee746b87d This patch addresses the problem of poor code generation for the zext ... v8i8 -> v8i32 on AVX machines. The codegen often scalarizes ANY_EXTEND nodes. The DAGCombiner has two optimizations that can mitigate the problem. First, if all of the operands of a BUILD_VECTOR node are extracted from an ZEXT/ANYEXT nodes, then it is possible to create a new simplified BUILD_VECTOR which uses UNDEFS/ZERO values to eliminate the scalar ZEXT/ANYEXT nodes. Second, another dag combine optimization lowers BUILD_VECTOR into a shuffle vector instruction. In the case of zext v8i8->v8i32 on AVX, a value in an XMM register is to be shuffled into a wide YMM register. This patch modifes the second optimization and allows the creation of shuffle vectors even when the newly generated vector and the original vector from which we extract the values are of different types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150340 91177308-0d34-0410-b5e6-96231b3b80d8		2012-02-12 15:05:31 +00:00
..
useful-harnesses
2009-01-01-BrCond.ll
2010-04-07-DbgValueOtherTargets.ll	If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.	2010-12-06 22:39:26 +00:00
and_ops.ll	Reapply r143206, with fixes. Disallow physical register lifetimes	2011-11-03 21:49:52 +00:00
arg_ret.ll	Fix memory access lowering on SPU, adding	2010-11-12 10:14:03 +00:00
bigstack.ll	Have SPU handle halfvec stores aligned by 8 bytes.	2010-08-09 16:33:00 +00:00
bss.ll	Be nice to Xcore and the XMOS assembler and avoid quoting section names	2011-03-04 20:03:14 +00:00
call.ll	Remove histogram tests.	2011-11-12 22:39:40 +00:00
crash.ll	teach cellspu how to return i8 and i16 from calls,	2010-04-20 05:36:09 +00:00
ctpop.ll
dg.exp
div_ops.ll	Division by pow-of-2 is not cheap on SPU, do it with	2010-11-23 13:27:59 +00:00
dp_farith.ll	Delete useless trailing semicolons.	2010-01-05 17:55:26 +00:00
eqv.ll	manually upgrade a bunch of tests to modern syntax, and remove some that	2011-06-17 03:14:27 +00:00
extract_elt.ll
fcmp32.ll	Allow for 'fcmp ogt' in SPU.	2010-11-24 11:42:17 +00:00
fcmp64.ll
fdiv.ll
fneg-fabs.ll
i8ops.ll
i64ops.ll
icmp8.ll
icmp16.ll
icmp32.ll
icmp64.ll
immed16.ll
immed32.ll	Don't feed 19 bit immediates to ILA.	2010-12-17 09:36:09 +00:00
immed64.ll
int2fp.ll
intrinsics_branch.ll
intrinsics_float.ll
intrinsics_logical.ll
jumptable.ll	Mark 'branch indirect' instruction as an indirect branch.	2011-10-13 11:40:03 +00:00
loads.ll	Allow load from constant on SPU.	2011-03-04 12:00:11 +00:00
mul_ops.ll	Teach dag combine to fold the following transformation more aggressively:	2010-01-06 19:38:29 +00:00
mul-with-overflow.ll	manually upgrade a bunch of tests to modern syntax, and remove some that	2011-06-17 03:14:27 +00:00
nand.ll	Reapply r143206, with fixes. Disallow physical register lifetimes	2011-11-03 21:49:52 +00:00
or_ops.ll	Reapply r143206, with fixes. Disallow physical register lifetimes	2011-11-03 21:49:52 +00:00
private.ll	make the asmparser reject function and type redefinitions. 'Merging' hasn't been	2011-06-17 07:06:44 +00:00
rotate_ops.ll	This patch addresses the problem of poor code generation for the zext	2012-02-12 15:05:31 +00:00
select_bits.ll	Reapply r143206, with fixes. Disallow physical register lifetimes	2011-11-03 21:49:52 +00:00
sext128.ll	Allow sign-extending of i8 and i16 to i128 on SPU.	2011-01-20 15:49:06 +00:00
shift_ops.ll	Enable element promotion type legalization by deafault.	2011-10-16 20:31:33 +00:00
shuffles.ll	Enable element promotion type legalization by deafault.	2011-10-16 20:31:33 +00:00
sp_farith.ll
stores.ll	Allow load from constant on SPU.	2011-03-04 12:00:11 +00:00
storestruct.ll	"on the rare occasion the SPU BE produces illegal assembly - it tries to emit an add instruction of the form 'a reg, reg, imm'."	2010-05-04 17:58:46 +00:00
struct_1.ll	Reapply r143206, with fixes. Disallow physical register lifetimes	2011-11-03 21:49:52 +00:00
sub_ops.ll	Fix encoding of 'sf' and 'sfh' instructions.	2010-05-10 08:13:49 +00:00
trunc.ll
v2f32.ll	don't test for codegen of 'store undef'	2011-04-09 02:31:26 +00:00
v2i32.ll	Enable element promotion type legalization by deafault.	2011-10-16 20:31:33 +00:00
vec_const.ll
vecinsert.ll	Fix SPU to cope with vector insertelement to an undef position.	2010-06-09 09:58:17 +00:00