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llvm-6502/lib/Target/Sparc
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Chris Lattner 302601c343 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25843 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 07:37:20 +00:00
..
.cvsignore ignore generated files 2005-09-07 23:47:44 +00:00
DelaySlotFiller.cpp Remove trailing whitespace 2005-04-21 23:30:14 +00:00
FPMover.cpp If the target has V9 instructions, this pass is a noop, don't bother 2006-01-30 05:51:14 +00:00
Makefile Add trivial subtarget support 2006-01-26 06:51:21 +00:00
README.txt add a note 2006-01-31 07:37:20 +00:00
Sparc.h treat conditional branches the same way as conditional moves (giving them 2006-01-31 06:56:30 +00:00
Sparc.td Subtarget feature can now set any variable to any value 2006-01-27 08:09:42 +00:00
SparcAsmPrinter.cpp compactify all of the integer conditional moves into one instruction that takes 2006-01-31 06:49:09 +00:00
SparcInstrFormats.td Push ops list, asm string, and pattern all the way up to InstV8. Move the 2005-12-18 08:21:00 +00:00
SparcInstrInfo.cpp Tighten up some checks 2005-12-18 06:40:34 +00:00
SparcInstrInfo.h Remove trailing whitespace 2005-04-21 23:30:14 +00:00
SparcInstrInfo.td add conditional moves of float and double values on int/fp condition codes. 2006-01-31 07:26:55 +00:00
SparcISelDAGToDAG.cpp treat conditional branches the same way as conditional moves (giving them 2006-01-31 06:56:30 +00:00
SparcRegisterInfo.cpp New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace 2006-01-09 18:28:21 +00:00
SparcRegisterInfo.h Pass extra regclasses into spilling code 2005-09-30 01:29:42 +00:00
SparcRegisterInfo.td Reserve G1 for frame offset stuff and use it to handle large stack frames. 2005-12-20 07:56:31 +00:00
SparcSubtarget.cpp Two changes: 2006-01-30 04:57:43 +00:00
SparcSubtarget.h Rest of subtarget support, remove references to ppc 2006-01-26 07:22:22 +00:00
SparcTargetMachine.cpp Add trivial subtarget support 2006-01-26 06:51:21 +00:00
SparcTargetMachine.h Add trivial subtarget support 2006-01-26 06:51:21 +00:00

README.txt 

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.