Tom Stellard 334ebf33ea R600/SI: Make SIInstrInfo::isOperandLegal() more strict ... A register operand that has a common sub-class with its instruction's defined register class is not always legal. For example, SReg_32 and M0Reg both have a common sub-class, but we can't use an SReg_32 in instructions that expect a M0Reg. This prevents the llvm.SI.sendmsg.ll test from failing when the fold operand pass is added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222368 91177308-0d34-0410-b5e6-96231b3b80d8		2014-11-19 16:58:49 +00:00
..
AsmParser	R600/SI: Start implementing an assembler	2014-11-14 14:08:00 +00:00
InstPrinter
MCTargetDesc
TargetInfo
AMDGPU.h
AMDGPU.td	R600/SI: Start implementing an assembler	2014-11-14 14:08:00 +00:00
AMDGPUAlwaysInlinePass.cpp
AMDGPUAsmPrinter.cpp
AMDGPUAsmPrinter.h
AMDGPUCallingConv.td
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUInstrInfo.cpp
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td	R600/SI: Combine min3/max3 instructions	2014-11-14 20:08:52 +00:00
AMDGPUInstructions.td	R600/SI: Start implementing an assembler	2014-11-14 14:08:00 +00:00
AMDGPUIntrinsicInfo.cpp
AMDGPUIntrinsicInfo.h
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp
AMDGPUISelLowering.cpp	R600: Permute operands when selecting legacy min/max	2014-11-15 05:02:57 +00:00
AMDGPUISelLowering.h	R600: Factor i64 UDIVREM lowering into its own fuction	2014-11-15 01:07:53 +00:00
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h
AMDGPUMCInstLower.cpp
AMDGPUMCInstLower.h
AMDGPUPromoteAlloca.cpp
AMDGPURegisterInfo.cpp
AMDGPURegisterInfo.h
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp
AMDGPUSubtarget.h
AMDGPUTargetMachine.cpp	R600/SI: Move SIFixSGPRCopies to inst selector passes	2014-11-18 21:06:58 +00:00
AMDGPUTargetMachine.h
AMDGPUTargetTransformInfo.cpp
AMDILCFGStructurizer.cpp
CaymanInstructions.td
CMakeLists.txt	R600/SI: Start implementing an assembler	2014-11-14 14:08:00 +00:00
EvergreenInstructions.td
LLVMBuild.txt	R600/SI: Start implementing an assembler	2014-11-14 14:08:00 +00:00
Makefile	R600/SI: Start implementing an assembler	2014-11-14 14:08:00 +00:00
Processors.td
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td	R600/SI: Start implementing an assembler	2014-11-14 14:08:00 +00:00
R600InstrInfo.cpp
R600InstrInfo.h
R600Instructions.td	R600/SI: Start implementing an assembler	2014-11-14 14:08:00 +00:00
R600Intrinsics.td
R600ISelLowering.cpp	R600: Factor i64 UDIVREM lowering into its own fuction	2014-11-15 01:07:53 +00:00
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp
R600Packetizer.cpp
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp
R700Instructions.td
SIAnnotateControlFlow.cpp
SIDefines.h
SIFixSGPRCopies.cpp	R600/SI: Assume SIFixSGPRCopies makes changes	2014-11-17 21:11:34 +00:00
SIFixSGPRLiveRanges.cpp
SIInsertWaits.cpp
SIInstrFormats.td	R600/SI: Set hasSideEffects = 0 on load and store instructions.	2014-11-18 23:57:33 +00:00
SIInstrInfo.cpp	R600/SI: Make SIInstrInfo::isOperandLegal() more strict	2014-11-19 16:58:49 +00:00
SIInstrInfo.h	R600/SI: Implement areMemAccessesTriviallyDisjoint	2014-11-19 00:01:31 +00:00
SIInstrInfo.td	R600/SI: Set hasSideEffects = 0 on load and store instructions.	2014-11-18 23:57:33 +00:00
SIInstructions.td	R600/SI: Mark s_movk_i32 as rematerializable	2014-11-14 20:43:28 +00:00
SIIntrinsics.td
SIISelLowering.cpp	R600/SI: Make sure resource descriptors are always stored in SGPRs	2014-11-18 20:39:39 +00:00
SIISelLowering.h	R600/SI: Combine min3/max3 instructions	2014-11-14 20:08:52 +00:00
SILoadStoreOptimizer.cpp
SILowerControlFlow.cpp
SILowerI1Copies.cpp	R600/SI: Fix verifier error from a branch on IMPLICIT_DEF	2014-11-14 18:43:41 +00:00
SIMachineFunctionInfo.cpp
SIMachineFunctionInfo.h
SIRegisterInfo.cpp	R600/SI: Fix spilling of m0 register	2014-11-14 20:43:26 +00:00
SIRegisterInfo.h
SIRegisterInfo.td	R600/SI: Fix assembly names for exec_hi and exec_lo	2014-11-14 14:08:04 +00:00
SISchedule.td
SIShrinkInstructions.cpp
SITypeRewriter.cpp