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https://github.com/c64scene-ar/llvm-6502.git
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3bd39d4ca8
registers if used by a bitconvert or using a bitconvert. This allows us to avoid constant pool loads and use cheaper integer instructions when the values come from or end up in integer regs anyway. For example, we now compile CodeGen/X86/fp-in-intregs.ll to: _test1: movl $2147483648, %eax xorl 4(%esp), %eax ret _test2: movl $1065353216, %eax orl 4(%esp), %eax andl $3212836864, %eax ret Instead of: _test1: movss 4(%esp), %xmm0 xorps LCPI2_0, %xmm0 movd %xmm0, %eax ret _test2: movss 4(%esp), %xmm0 andps LCPI3_0, %xmm0 movss LCPI3_1, %xmm1 andps LCPI3_2, %xmm1 orps %xmm0, %xmm1 movd %xmm1, %eax ret bitconverts can happen due to various calling conventions that require fp values to passed in integer regs in some cases, e.g. when returning a complex. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46414 91177308-0d34-0410-b5e6-96231b3b80d8 |
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| .. | ||
| CallingConvLower.cpp | ||
| DAGCombiner.cpp | ||
| LegalizeDAG.cpp | ||
| LegalizeTypes.cpp | ||
| LegalizeTypes.h | ||
| LegalizeTypesExpand.cpp | ||
| LegalizeTypesPromote.cpp | ||
| LegalizeTypesScalarize.cpp | ||
| LegalizeTypesSplit.cpp | ||
| Makefile | ||
| ScheduleDAG.cpp | ||
| ScheduleDAGList.cpp | ||
| ScheduleDAGRRList.cpp | ||
| SelectionDAG.cpp | ||
| SelectionDAGISel.cpp | ||
| SelectionDAGPrinter.cpp | ||
| TargetLowering.cpp | ||